2-12.Edge Exclusion
The outer annulus of the wafer is designated as wafer handling area and is excluded from surface nish criteria (such as scratches, pits, haze, contamination, craters,dimples, grooves, mounds, orange peel and saw marks). This annulus is 2 mm for 76.2 mm substrates, and 3 mm for 100.0 mm substrates.
5-6-4-1 SiC High-Power Rectifiers The high-power diode rectifier is a critical building block of power conversion circuits. Recent reviews of experimental SiC rectifier results are given in References 3, 134, 172, 180, and 181. Most important SiC diode rectifier device design trade-offs roughly parallel well-known [...]
3-7. ID Correct and Major Wafer Flat Both should be readily discernible.
3-2. Scratches Grooves or cuts below the surface plane of the wafer having a length-to-width ratio of greater than 5 to 1. Scratches are speci ed by the number of discrete scratches times the total length in fractional diameter.
5-2-2-2 SiC Semiconductor Electrical Properties Owing to the differing arrangement of Si and C atoms within the SiC crystal lattice, each SiC polytype exhibits unique fundamental electrical and optical properties. Some of the more important semiconductor electrical properties of the 3C, 4H, and 6H SiC polytypes are [...]
2-22.Surface Roughness Often shortened to roughness, is a measure of the texture of a surface. It is quantified by the vertical deviations of a real surface from its ideal form. If these deviations are large, the surface is rough; if they are small the surface [...]
5-6-4-1-1 SiC Schottky Power Rectifiers. 4H-SiC power Schottky diodes (with rated blocking voltages up to 1200 V and rated on-state currents up to 20 A as of this writing) are now commercially available . The basic structure of these unipolar diodes is a patterned metal [...]
