2-12.Edge Exclusion
The outer annulus of the wafer is designated as wafer handling area and is excluded from surface nish criteria (such as scratches, pits, haze, contamination, craters,dimples, grooves, mounds, orange peel and saw marks). This annulus is 2 mm for 76.2 mm substrates, and 3 mm for 100.0 mm substrates.
3-5. Backside Cleanliness Veri ed by inspecting for a uniform color to the wafer backside. Note there is a darker region near the center of some higher doped wafers. Backside cleanliness speci ed as percent area clean.
2-32.Semi-insulating Semi-insulating Doping with the impurities vanadium creates semi-insulating material of silicon carbide.
2-20.Linear Crystallographic Defects Crystalline solids exhibit a periodic crystal structure. The positions of atoms or molecules occur on repeating fixed distances, determined by the unit cell parameters. However, the arrangement of atom or molecules in most crystalline materials is not perfect. The regular patterns are [...]
5-5-6 SiC Device Packaging and System Considerations Hostile-environment SiC semiconductor devices and ICs are of little advantage if they cannot be reliably packaged and connected to form a complete system capable of hostile-environment operation. With proper material selection, modifications of existing IC packaging technologies appear [...]
2-22.Surface Roughness Often shortened to roughness, is a measure of the texture of a surface. It is quantified by the vertical deviations of a real surface from its ideal form. If these deviations are large, the surface is rough; if they are small the surface [...]
5-4-4-2 SiC Epitaxial Growth Polytype Control Homoepitaxial growth, whereby the polytype of the SiC epilayer matches the polytype of the SiC substrate, is accomplished by “step-controlled” epitaxy . Step-controlled epitaxy is based upon growing epilayers on an SiC wafer polished at an angle (called the [...]
