2-12.Edge Exclusion
The outer annulus of the wafer is designated as wafer handling area and is excluded from surface nish criteria (such as scratches, pits, haze, contamination, craters,dimples, grooves, mounds, orange peel and saw marks). This annulus is 2 mm for 76.2 mm substrates, and [...]
2018-06-28meta-author
5-1 Introduction
Silicon carbide (SiC)-based semiconductor electronic devices and circuits are presently being developed
for use in high-temperature, high-power, and high-radiation conditions under which conventional semiconductors
cannot adequately perform. Silicon carbide’s ability to function under such extreme conditions
is expected to enable significant improvements to a far-ranging variety [...]
2018-06-28meta-author
5-3-2 High-Power Device Operation
The high breakdown field and high thermal conductivity of SiC coupled with high operational junction
temperatures theoretically permit extremely high-power densities and efficiencies to be realized in SiC
devices. The high breakdown field of SiC relative to silicon enables the blocking voltage region [...]
2018-06-28meta-author
2-19.Scratches
A scratch is dened as a singular cut or groove into the frontside wafer surface with a length-to-width ratio of greater than 5 to 1, and visible under hight intensity illumination.
2018-06-28meta-author
5-2-2-2 SiC Semiconductor Electrical Properties
Owing to the differing arrangement of Si and C atoms within the SiC crystal lattice, each SiC polytype
exhibits unique fundamental electrical and optical properties. Some of the more important semiconductor
electrical properties of the 3C, 4H, and 6H SiC polytypes are [...]
2018-06-28meta-author
5-5-3 SiC Contacts and Interconnect
All useful semiconductor electronics require conductive signal paths in and out of each device as well as
conductive interconnects to carry signals between devices on the same chip and to external circuit
elements that reside off-chip. While SiC itself is theoretically capable [...]
2018-06-28meta-author