3-2. Scratches
Grooves or cuts below the surface plane of the wafer having a length-to-width ratio of greater than 5 to 1. Scratches are speci ed by the number of discrete scratches times the total length in fractional diameter.
2018-06-28meta-author
5-7 Future of SiC
It can be safely predicted that SiC will never displace silicon as the dominant semiconductor used for the manufacture of the vast majority of the world’s electronic chips that are primarily low-voltage digital and analog chips targeted for operation in normal [...]
2018-06-28meta-author
5-2-1-1 SiC Crystallography
Silicon carbide occurs in many different crystal structures, called polytypes. Despite the fact that all SiC polytypes chemically consist of 50% carbon atoms covalently bonded with 50% silicon atoms, each SiC polytype has its own distinct set of electrical semiconductor properties. While [...]
2018-06-28meta-author
2-28.WARP
Warp is the difference between the maximum and the minimum distances of the median surface of a free, un-clamped wafer from the reference plane defined above. This definition follows ASTM F657, and ASTM F1390,which deviation from a plane of a slice or wafer centerline [...]
2018-06-28meta-author
Most SiC electronic devices are not fabricated directly in sublimation-grown wafers, but are instead fabricated in much higher quality epitaxial SiC layers that are grown on top of the initial sublimation grown wafer. Well-grown SiC epilayers have superior electrical properties and are more controllable [...]
2018-06-28meta-author
2-21.Usable Area
A cumulative subtraction of all noted defect areas from the frontside wafer quality area within the edge exclusion zone. The remaining percent value indicates the proportion of the frontside surface to be free of all noted defects (does not include edge exclusion).
2018-06-28meta-author