2-34.Chemical Mechanical Polishing
Chemical Mechanical Polishing/Planarization is short as CMP, a process of smoothing surfaces with the combination of chemical and mechanical forces. It can be thought of as a hybrid of chemical etching and free abrasive polishing.
2-2.Wafer Thickness, Center Point Thin (thickness depends on wafer diameter, but is typically less than 1mm),circular slice of single-crystal semiconductor material cut from the ingot of single crystal semiconductor; used in manufacturing of semiconductor devices and integrated circuits; wafer diameters may range from 5mm to [...]
5-5 SiC Device Fundamentals To minimize the development and production costs of SiC electronics, it is important that SiC device fabrication takes advantage of existing silicon and GaAs wafer processing infrastructure as much as possible. As will be discussed in this section, most of the [...]
5-2-1-2 Electrical Properties Owing to the differing arrangement of Si and C atoms within the SiC crystal lattice, each SiC polytype exhibits unique fundamental electrical and optical properties. Some of the more important semiconductor electrical properties of the 3C, 4H, and 6H SiC polytypes are given in [...]
3-1. Large Point Defects Defects which exhibit a clear shape to the unassisted eye and are > 50 microns across. These features include spikes, adherent particles, chips and craters. Large point defects less than 3 mm apart count as one defect.
2-5.Misorientation In wafers cut intentionally “off orientation”, the angle between the projection of the normal vector to the wafers surface onto a {0001} plane and the projection on that plane of the nearest <11-20> direction.
5-4-2 Growth of 3C-SiC on Large-Area (Silicon) Substrates Despite the absence of SiC substrates, the potential benefits of SiC hostile-environment electronics nevertheless drove modest research efforts aimed at obtaining SiC in a manufacturable wafer form.Toward this end, the heteroepitaxial growth of single-crystal SiC layers on [...]
