2-4.Wafer Surface Orientation
Denotes the orientation of the surface of a wafer with respect to a crystallographic plane within the lattice structure.
In wafers cut intentionally “off orientation”, the direction of cut is parallel to the primary at, away from the secondary at.
Measured with [...]
2018-06-28meta-author
5-6-4-1-1 SiC Schottky Power Rectifiers.
4H-SiC power Schottky diodes (with rated blocking voltages up to 1200 V and rated on-state currents up to 20 A as of this writing) are now commercially available . The basic structure of these unipolar diodes is a patterned metal [...]
2018-06-28meta-author
5-3-1 High-Temperature Device Operation
The wide bandgap energy and low intrinsic carrier concentration of SiC allow SiC to maintain
semiconductor behavior at much higher temperatures than silicon, which in turn permits SiC semiconductor
device functionality at much higher temperatures than silicon . As discussed in basic
semiconductor electronic [...]
2018-06-28meta-author
2-11.Edge Chips
Any edge anomalies (including wafer saw exit marks) in excess of 1.0 mm in either radial depth or width. As viewed under diffuse illumination, edge chips are determined as unintentionally missing material from the edge of the wafer.
2018-06-28meta-author
5-4 SiC Semiconductor Crystal Growth
As of this writing, much of the outstanding theoretical promise of SiC electronics highlighted in the
previous section has largely gone unrealized. A brief historical examination quickly shows that serious
shortcomings in SiC semiconductor material manufacturability and quality have greatly hindered the
development [...]
2018-06-28meta-author
2-12.Edge Exclusion
The outer annulus of the wafer is designated as wafer handling area and is excluded from surface nish criteria (such as scratches, pits, haze, contamination, craters,dimples, grooves, mounds, orange peel and saw marks). This annulus is 2 mm for 76.2 mm substrates, and [...]
2018-06-28meta-author