3-4. Step Bunching
Step bunching is visible as a pattern of parallel lines running perpendicular to the major at. If present, estimate the % of speci ed area affected.
3-4. Step Bunching
Step bunching is visible as a pattern of parallel lines running perpendicular to the major at. If present, estimate the % of speci ed area affected.
2-37.Test Grade Test Grade: A silicon carbide wafer of lower quality than Prime, and used primarily for testing processes. SEMI indicates the bulk, surface, and physical properties required to label silicon carbide wafers as “Test Wafers”.
3-6. Edge Chips Areas where material has been unintentionally removed from the wafer.Do not confuse fractures in epi crown with edge chips.
5-4-4-2 SiC Epitaxial Growth Polytype Control Homoepitaxial growth, whereby the polytype of the SiC epilayer matches the polytype of the SiC substrate, is accomplished by “step-controlled” epitaxy . Step-controlled epitaxy is based upon growing epilayers on an SiC wafer polished at an angle (called the [...]
2-21.Usable Area A cumulative subtraction of all noted defect areas from the frontside wafer quality area within the edge exclusion zone. The remaining percent value indicates the proportion of the frontside surface to be free of all noted defects (does not include edge exclusion).
5-4-4-1 SiC Epitaxial Growth Processes An interesting variety of SiC epitaxial growth methodologies, ranging from liquid-phase epitaxy, molecular beam epitaxy, and chemical vapor deposition(CVD) have been investigated . The CVD growth technique is generally accepted as the most promising method for attaining epilayer reproducibility, quality, [...]
5-5-3 SiC Contacts and Interconnect All useful semiconductor electronics require conductive signal paths in and out of each device as well as conductive interconnects to carry signals between devices on the same chip and to external circuit elements that reside off-chip. While SiC itself is theoretically capable [...]