Research on Warpage Control Technology of 4H-SiC Wafer +

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4H-SiC is the core material of the new generation of power semiconductors, and the global flatness of wafers (including Bow and Warp) is the key factor affecting subsequent epitaxial growth and device yield. The warpage of substrate is caused by the combined effects of internal residual stress, surface damage, and process induced stress. To address this challenge, the industry has developed multi-level control strategies ranging from basic mechanical processing to advanced surface engineering.

1. Control Flatness of SiC Wafer by Optimized Grinding Sequence

Grinding sequence optimization is the core technology path to achieve high-precision flatness control of SiC wafers, and its design is based on the significant difference in material mechanical properties between the C and Si surfaces of SiC wafers. The C surface has a higher hardness (about 35GPa), resulting in a surface damage layer thickness of up to 15-20μm after cutting processing. The fracture toughness of the Si surface is 20% -30% higher than that of the C surface, making it easier to achieve surface quality control through plastic deformation (see Fig. 1). This anisotropic characteristic directly determines the optimization direction of the grinding sequence: in the coarse grinding stage, the C surface should be prioritized for efficient removal of thick damage layers, while in the fine grinding stage, the Si surface should be processed first before the C surface, utilizing the high toughness of the Si surface to buffer subsequent processing stresses and reduce final surface defects.

Fig. 1 (a) Hardness and (b) fracture toughness KIC values of Si and C surfaces of 4H-SiC substrates after SAW, coarse grinding (CL), and fine grinding (FL)

Zhang et al. conducted comparative experiments on the effect of different grinding sequences on warpage control. The results showed that after the complete grinding process, Process B technology can control the global flatness (GBIR) of the chip within 3μm, which is 27% higher than Process A technology. In addition, the depth of the subsurface damage layer is reduced to below 3μm, laying a good foundation for subsequent polishing processes (see Fig. 2 and 3). This sequence optimization strategy based on material anisotropy has become a standard technical solution in the mass production and processing of 4H-SiC substrates.

Fig. 2 Schematic diagram of grinding sequence: Process A – Si surface first, then C surface; Process B – First C surface, then Si surface

Fig. 3 Changes in Bow and Warp Values of 4H-SiC Cutting Slices after Process A and Process B

2. Dynamic Thermal Annealing Technology in Controlling the Warpage of SiC Substrates

Dynamic annealing technology promotes the sublimation and recrystallization of SiC surface atoms under high temperature and pressure through the synergistic effect of dynamic temperature and pressure fields, achieving precise control of warpage and improvement of flatness. This technology adopts a two-step approach: first, high-temperature annealing eliminates macroscopic bending and surface damage, and then low-temperature vacuum etching reduces roughness.

Toda used this process to machine SiC wafers, and the experiment found that the roughness of the Si surface of the substrate decreased from 166nm to 54nm, the depth of the damage layer decreased from above 200nm to below 50nm, the grain orientation became more consistent, and dislocations were basically eliminated. Dynamic thermal annealing technology effectively avoids secondary warpage, achieving a yield of 92% with warpage controlled within 5μm, making it a key process for optimizing SiC substrate warpage, surface quality, and crystal integrity.

Fig. 4 Sa values on the (a) Si and (b) C surfaces, as well as the total thickness variation of each substrate cut by MWS (loose abrasive) under four different temperature and pressure conditions due to dynamic annealing effects. The laser microscope images (i) – (iv) and (i ‘) – (iv’) represent the surface morphology after Dynamic annealing treatment under each condition.

3. Double Sided Epitaxial Deposition Technology for Regulating the Curvature of SiC Wafers before Epitaxial Growth

Double sided epitaxial deposition (Dynamic AGE-ing®, DA) technology focuses on stress balance and achieves precise control of warpage by implementing differentiated processes on the Si and C surfaces of SiC wafers. The principle is that etching on the Si surface releases the original compressive stress, while epitaxial growth on the C surface introduces controllable tensile stress. The two are dynamically balanced to achieve linear control of warpage. Compared to traditional single-sided CVD epitaxy, DA technology significantly expands the control range.

Fig. 5 Schematic diagram of simultaneously controlling both sides of SiC wafer using DA technology

DA adopts a differentiation strategy for different initial warpage states: the wafer with positive bow introduces tensile stress through C-plane growth to reduce the bow value; wafers of negative bow release compressive stress through Si surface etching to increase the bow value. This technology is particularly suitable for large-sized wafers, such as an 8-inch SiC wafer optimized from -11.96μm to -0.37μm after DA process, with an improvement of 97%, as shown in Fig. 6.

Fig. 6 Warp control results of 8-inch SiC wafer by DA process

It should be noted that the surface damage layer on the wafer has a significant impact on the control effect. When the epitaxial thickness of the C-plane is less than 120nm, the bow value will abnormally increase due to rapid relaxation of surface damage layer. Therefore, in actual processes, it is necessary to control the epitaxial thickness to be ≥120nm or optimize surface damage layer pretreatment to avoid stress imbalance.

DA technology, with its dual sided collaborative stress regulation mechanism, effectively breaks through the limitations of traditional single-sided processes and provides an efficient solution for warpage control of large-sized SiC substrates. It has important application prospects in the large-scale manufacturing of third-generation semiconductors.

The control of warpage in 4H-SiC wafer is a multi-factor, multi-process collaborative system engineering. From sequence optimization of mechanical grinding, to dynamic thermal annealing, and to active control of double-sided epitaxy/etching, researchers have proposed effective solutions from different dimensions. In the future, with the popularization of 8-inch wafers, the combination of Dynamic type active control technology and non-destructive testing methods such as LLS will provide more possibilities for achieving “zero warpage” SiC substrates.

Whether you need 4H-SiC wafer for research or for industrial applications, please contact us email at [email protected] and [email protected].

 

References：

1. Zhang, X., Liu, X., Wang, Y., Zhu, R., Zhang, X., Zhang, Y., … & Pi, X. (2023). Optimizing the flatness of 4H-silicon carbide wafers by tuning the sequence of lapping. Semiconductor Science and Technology, 38(3), 034001.
2. Toda, K., Kakutani, D., Dojima, D., Nakajima, Y., Mihara, H., & Kaneko, T. (2024, August). A Novel Contactless SiC Wafer Planarization Processing after Mechanical Slicing by Dynamic Thermal Annealing Processes. In Materials Science Forum (Vol. 1124, pp. 77-84). Trans Tech Publications Ltd.
3. Dojima, D., Jeong, S., Toda, K., & Kaneko, T. (2025, September). Development of a Novel Warpage Control Method for Epi-Ready 4H-SiC Wafers by Depositing Homoepitaxial Layers on both Si-and C-Faces. In Materials Science Forum (Vol. 1156, pp. 75-81). Trans Tech Publications Ltd.