SiC Epilayers

SiC Epilayers

Most SiC electronic devices are not fabricated directly in sublimation-grown wafers, but are instead fabricated in much higher quality epitaxial SiC layers that are grown on top of the initial sublimation grown wafer. Well-grown SiC epilayers have superior electrical properties and are more controllable and reproducible than bulk sublimation-grown SiC wafer material. Therefore, the controlled growth of high-quality epilayer is highly important in the realization of useful SiC electronics. As one of leading epitaxial wafer manufacturers, PAM-XIAMEN can perform SiC epitaxy on SiC substrate. Detail specifications please take SiC wafer with epitaxial film below for example:

SiC Epilayer

1. Specification of SiC Epi Layer Structure PAMP16192-SIC

2″ diameter SiC



4 degrees off

300-500um thickness


Double side polished, and the orientation for semi-insulating is C (0001)

Epitaxial film:

1um thick

No intentional doping


Si face or carbon face is not relative with semi-insulating, normally it is Si face polished, epi-ready. Or we said C (0001) orientation. Also for semi-insulating, C (0001) is for the mainstream, and all the substrate manufacturers are doing on axis, not 4 degree off;

4 degree off is required in order to perform good quality SiC epitaxy on the SiC wafer.

2. Paramerters for 4H-SiC Epilayers

The lowest electron concentration ever published is around 1E14cm3. It usually requires special growth parameters which generate more surface defects in the layer.

We measure CV (carrier concentration) and calculate the resistivity in the most popular way. For the attached AFM of undoped SiC epi film, the concentration was 1E15cm3.

4H-SiC Epilayers AFM 4H-SiC Epilayers AFM

3. Dopant in SiC Substrate and Epilayer

For the specification of SiC epitaxial layer on semi-insulating SiC substrate talked above, one big concern from customer is that the unintentional incorporation of nitrogen, vanadium or other dopants will make the wafer epi layer, buffer layer n-type during the epitaxial growth.

Actually, there is no need for a buffer layer as the substrate is semi-insulating, and this is homo-epitaxy (SiC on SiC). Better undoped substrate but in case of vanadium it still works. The diffusion coefficient in SiC is extremely low. Besides, Nitrogen as the impurity is always present in the undoped epi SiC and the layer is always n-type. The matter is how much doped. And we can guarantee that it will be as low as possible without degrading the surface/crystal. 

4. Characterization for Surface of SiC Epi Wafer

Observed through above AFM image, the surface with ridges looks very rough, which is caused by step bunching. Step-bunching is always present but we can control the step height in some range. That was an example where we wanted to get a good structural quality of the layer. The SiC substrate roughness will be always lower after polishing but the structural (crystalographic) quality of such surface is very poor. If you want to produce a good device, the step bunching effect is “necessary” and it does not influence device performance. For example, we use 10nm roughness for graphene growth. Attached another AFM result for your reference:

For specific purposes, the smooth epilayer is more important. The roughness of SiC epi-layer contains two parameters: micro-steps and macro-steps connected to step-bunching. We will control the the two parameters in the epi wafer manufacturing process to get smoother epilayer surface and meet your needs.


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