5-5-4 Patterned Etching of SiC for Device Fabrication

At room temperature, there are no known conventional wet chemicals that etch single-crystal SiC. Most

patterned etching of SiC for electronic devices and circuits is accomplished using dry etching techniques.

The reader should consult References 122–124 which contain summaries of dry SiC etching results

obtained to date. The most commonly employed process involves reactive ion etching (RIE) of SiC in

fluorinated plasmas. Sacrificial etch masks (such as aluminum metal) are deposited and photolithographically

patterned to protect desired areas from being etched. The SiC RIE process can be implemented

using standard silicon RIE hardware and typical 4H- and 6H-SiC RIE etch rates of the order of hundreds

of angstroms per minute. Well-optimized SiC RIE processes are typically highly anisotropic with little

undercutting of the etch mask, leaving smooth surfaces. One of the keys to achieving smooth surfaces

is preventing “micromasking”, wherein the masking material is slightly etched and randomly redeposited

onto the sample effectively masking very small areas on the sample that were intended for uniform

etching. This can result in “grass”-like etch-residue features being formed in the unmasked regions, which

is undesirable in most cases.

While RIE etch rates are sufficient for many electronic applications, much higher SiC etch rates are

necessary to carve features of the order of tens to hundreds of micrometers deep that are needed to realize

advanced sensors, MEMS, and through-wafer holes useful for SiC RF devices. High-density plasma dryetching

techniques such as electron cyclotron resonance and inductively coupled plasma have been

developed to meet the need for deep etching of SiC. Residue-free patterned etch rates exceeding a

thousand angstroms a minute have been demonstrated .

Patterned etching of SiC at very high etch rates has also been demonstrated using photo-assisted and

dark electrochemical wet etching . By choosing proper etching conditions, this technique has demonstrated

a very useful dopant-selective etch-stop capability. However, there are major incompatibilities of the

electrochemical process that make it undesirable for VLSI mass production, including extensive

preetching and postetching sample preparation, etch isotropy and mask undercutting, and somewhat

nonuniform etching across the sample. Laser etching techniques are capable of etching large features,

such as via through-wafer holes useful for RF chips .