The Value of Notch: 8-inch P-Type Silicon Substrate for Power MOSFETs
In the manufacturing process of semiconductor devices such as power MOSFETs, the silicon substrate for power MOSFET is not only the structural support layer but also the core material that determines electrical performance and reliability. Beyond traditional indicators like resistivity uniformity, surface roughness, and crystal defects, the design and processing quality of Notch – the positioning gap – has a significant impact on automation efficiency, process consistency, and final yield.
1. The Core Value of Notch
Notch is a small groove located at the edge of the wafer, which provides precise positioning and orientation reference for automation equipment in semiconductor manufacturing. Its core values are reflected in the following four aspects:
1.1 Accurate Positioning and Orientation
Notch orientation serves as the angular reference point for all automated processing tools – photolithography, etching, ion implantation, and thin film deposition. An optical detection system identifies the Notch position, enabling the equipment to rotate the wafer to a preset orientation with sub-micron alignment accuracy.
1.2 Identify Crystal Orientation
Notch accurately calibrates the crystal orientation of the silicon wafer, such as <100> or <111>. For power MOSFETs, the <100> crystal orientation offers the highest electron mobility and excellent consistency with thermal oxidation growth rates. Thus, the precision of Notch labeling directly affects the electrical uniformity of the device channel region.
1.3 Improve Production Efficiency and Yield
Compared to the flat edges used on older silicon wafers, Notch reduces the occupation of the effective wafer area (typically increasing usable area by ~3%). Its symmetric structure is better suited for high-speed, high-precision automated wafer handling. Precision Notch machining, combined with edge polishing technology, significantly reduces particle defects and breakage risks caused by edge chipping or cracks – thereby improving overall manufacturing yield.
1.4 Ensure process consistency
Many process tools (CVD, PVD, rapid thermal processing) need to adjust the spatial distribution of parameters – such as gas flow direction or plasma uniformity – based on the Notch position before processing. Accurate Notch positioning guarantees that every wafer experiences the same process environment, resulting in highly consistent film thickness, resistivity uniformity, and stress distribution.
Fig. 1 Notch geometric schematic diagram compliant with SEMI M1 standard
2. Technical Features of Notch on Silicon Substrate
The shape and size of Notch must comply with internationally recognized standards such as SEMI M1 notch standard to ensure compatibility and precise operation across different equipment manufacturers. The key Notch geometric parameters are summarized below:
| Parameters | Typical Values | Function and Influence |
| Depth（Vh） | 1.125 ±0.125mm | Ensure reliable triggering of optical sensors; Being too shallow can lead to detection failure, while being too deep can easily cause edge stress concentration. |
| Included angle（AngV） | 90°±5° | Define the geometric shape of the groove, which affects the mechanical clamping and optical recognition of the equipment. |
| Bottom curvature radius（Vr） | Smooth transition of design values | Reduce stress concentration and prevent crack initiation during high-speed transmission. |
| Corner radius（R1/R2） | Smooth arc transition | Further enhance edge resilience and reduce fragment risk. |
| Crystal parallelism | Relative to <110> direction, off-angle within ±1° | Ensures precise correspondence between Notch direction and crystal orientation – fundamental for photolithography alignment. |
3. 8-inch P-Type Silicon Substrate Specification for Power MOSFET
Based on the above technical considerations, the 8-inch P-type silicon substrate specification for power MOSFETs provided by PAM-XIAMEN includes the following key parameters
| Parameters | Typical Values |
| Diameter | 200±0.2mm |
| Thickness | 725 ±15µm |
| Orientation | <100> ±0.25° |
| Conductive Type/Doping | P/B |
| Resistivity | 8.5 – 11.5Ω·cm |
| Notch Orientation | <110>±1° |
| Notch depth | 1.125±0.125mm |
| RRV | ≤14% |
| TTV | ≤5µm |
| Warp | ≤60µm |
| SFQR (25×25 mm) | ≤0.15µm |
| EPD | ≤1cm⁻² |
| Metal pollution (Fe, Na, Cr, Ni, Zn, etc.) on front side | ≤1×1010cm⁻² |
| Front side roughness | ≤0.04µm |
| Back side roughness | 0.5–0.8µm |
| Localized Light-Scatterer (≥0.2µm) | ≤30 |
Note: The resistivity, thickness, and backside treatment can be customized according to customer needs.
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