For single photon detection technology, in addition to the traditional InP/InGaAs SPAD, new material systems such as low noise material systems constructed from Sb based digital alloys, multi multiplication InP/InGaAs SPAD using ionization engineering, and InAlAs/InGaAs SPAD have also been developed. PAM-XIAMEN can provide InP [...]
2023-07-12meta-author
Xiamen Powerway Advanced Material Co.,Ltd., a leading supplier of InGaAsN wafer and other related products and services announced the new availability of size 2″ is on mass production in 2017. This new product represents a natural addition to PAM-XIAMEN’s product line.
Dr. Shaka, said, “We [...]
2017-07-11meta-author
The ability to grow thin GaN layers on Si substrates has led to the development of lateral high power and high-speed devices such as GaN HEMTs. These devices have already demonstrated promising performance and have been adopted for mass market. But lateral devices require [...]
2020-01-20meta-author
PAM XIAMEN offers DyScO3/GdScO3//TbScO3 crystal.
Crystal
Structure /Lattice Constant(A)
MP oC
Density, g/cm3
Growth Tech
DyScO3
Orthorombic a=5.44 b=5.71 c=7.89
2127
6.9
CZ
GdScO3
Orthorombic a=5.45 b=5.75 c=7.93
2127
6.6
CZ
TbScO3
Orthorhombic, a = 5.4543, b = 5.7233 c = 7.9147
2127
6.6
CZ
DyScO3 (110) 5x5x0.5mm 1sp (PAM210322-DYSCO3)
DyScO3 (110) 5x5x0.5mm 1sp”
DyScO3 (110) 5x5x0.5mm 2sp
DyScO3 (110) 10x10x0.5mm 1sp
DyScO3 (110) 10x10x0.5mm 2sp
DyScO3 (001) 10x10x0.5mm 1sp [...]
2019-05-20meta-author
PAM XIAMEN offers 3″ FZ Prime Silicon Wafer.
3″ Si FZ
39-47Ωcm
about 1.5mil is etched from the surfaces in order to remove any surface damage
1.5mil = 1.5*25.4= 38.1μm
For more information, please visit our website: https://www.powerwaywafer.com,
send us email at sales@powerwaywafer.com and [...]
2019-07-01meta-author
The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device [...]
2020-01-13meta-author