940nm VCSEL Array with Single Emitter for Proximity Light Sensing

PAM-XIAMEN can offer 940nm VCSEL array chip with single emitter, which is mainly used for proximity light sensing in consumer electronics such as mobile phone front Proximity, TWS earphones, smartwatches/bracelets, etc. The parameters of 940nm VCSEL array with single emitter are shown as follows:

1. VCSEL Array Product Description & Features

Item No. PAM940V001K

· 940nm VCSEL Array

· 8.4mW @ 9mA

Number of emitters: 1

2. 940nm VCSLE Array Mechanical Characteristics

Number of emitters	1
Chip width	145±15um
Chip length	145±15um
Chip height	100±10um
Aperture	12±2um

 

3. 940nm VCSEL Chip Electro-Optical Characteristics

Parameters	Symbol	Min	Typical	Max	Units	Test Condition
Threshold current	Ith	–	1.3	–	mA	@9mA, 25℃, CW mode
Operating voltage	Vf	1.82	1.95	2.20	V
Wavelength	λpeak	930	940	950	nm
Output optical power	P	7.5	8.4	–	mW
Slope efficiency	ηs	–	1.1	–	W/A
Power conversion efficiency	PCE	42	48	–	%
Beam full divergence (D86)	φ		25
Wavelength Temp. coefficient	dλ/dT		0.07		nm/℃

 

4. Typical Performance Curves of 940nm VCSEL Array with 1 Emitter @9mA

5. Absolute Maximum Ratings of 940nm VCSEL Laser Array

Parameters	Conditions
Forward DC current	≤25mA
Storage temperature	-40 to 85℃
Packaging temperature	≤260℃(<10S)
Junction temperature	≤120℃

6. VCSEL Chip Process

The main process of VCSEL is divided into two main parts. One part is the implementation of metal organic chemical vapor deposition (MOCVD) technology with a thousand layer cake structure; One part is to implement the FAB wafer process for various backend structures and requirements, including photolithography, electrode evaporation deposition and stripping, wet bench etching, lateral wet oxidation, BCB filling, etc.

1) VCSEL Wafer MOCVD Epitaxy

In the MOCVD process, the reaction gas combines in the reactor at an elevated temperature to cause chemical interactions and deposit the material on the substrate. In MOCVD, ultrapure gas is injected into the reactor and finely measured to deposit very thin atomic layers onto semiconductor chips. The surface reaction of organic compounds or metal organic compounds containing the required chemical elements with hydrides creates conditions for crystal growth, forming epitaxy of materials and compound semiconductors. For VCSEL, it is generally necessary to grow multiple layers of reflection and emission layers on GaAs or InP wafers.

2) FAB Wafer Processes of VCSEL

2.1) P contact manufacturing

The general contact material for p contacts is Ti/Pt/Au, which is achieved by electron beam evaporation or metal evaporation followed by stripping.

2.2) First Mesa Etching and SiN Deposition

After completing the deposition of the poles, perform the first stage etching to expose the upper DBR reflection and excitation layers. This etching step is a chemical process, such as using ICP-RIE method combined with NF3 and SlCl4 for etching. After etching, a layer of SiN is deposited on the entire surface of the table by PECVD method. The layer of SiN can protect the Mesa surface and chip surface in the subsequent lateral oxidation process.

2.3) Lateral Oxidation

Firstly, the SiN on the side will be removed, followed by a lateral oxidation process, which is a crucial step in VCSEL manufacturing. In the wet oxidation process, the high aluminum component oxide layer in the epitaxial structure is transformed into low refractive index and high insulation Al2O3 through the wet oxidation process, forming effective light and electric field confinement. The size and shape of the oxide pore size affect many performance parameters of VCSEL devices, such as the threshold current, optical power, and series resistance of VCSEL. During the wet oxidation process, the oxidation rate is controlled by controlling the nitrogen gas flow rate and the heating temperature inside the chamber, ensuring the stability of the oxidation rate and achieving precise control of the oxidation pore size over time. At the same time, an infrared light source CCD is used to observe the oxidation situation in real time, ensuring the success rate of the oxidation process. The size and shape of the wet lateral oxidation pore size of VCSEL affect many performance of VCSEL devices, with a general limitation of pore size of 4-20um. The lateral structure shape of the VCSEL oxidation restriction layer is usually circular, so the light spot of VCSEL is basically circular.

After lateral oxidation, in order to prevent the AlAs layer in the oxidation process from continuing to oxidize inward and affecting the volume of the resonant cavity, causing sudden changes in laser characteristics, many VCSELs also add an insulation protection process (passification), using ALD method to deposit aluminum oxide (Al2O3) thin films with similar characteristics to the VCSEL oxide layer. This side coating is uniform, dense, and thin enough to completely insulate and protect the chip, and the stress is also small.

2.4) Second Mesa Etching

After completing the lateral oxidation pore size, etching was carried out using SiCl4 and ICP-RIE processes to form a second Mesa layer. The protected SiN layer was removed by ICP-RIE combined with NF3.

2.5) Manufacturing of N Contacts

The n contact is Ni/Ge/Au, achieved by electron beam evaporation or metal evaporation followed by stripping. After completion, anneal in an inert N2 environment (430 ℃).

2.6) Contact Layer Peeling

The contact layer outside the Mesa and n contacts is further peeled off to reduce the capacitance of the bond pad.

2.7) BCB filling

Spray a layer of BCB (benzocyclobutene) onto the entire VCSEL chip using a spray coating method, making the entire VCSEL flat.

2.8) Bondpad Deposition

Depositing Ti/Au bond pad to connect it to the n/p electrode contact.

Different types of VCSEL may have some differences in the steps, but they are basically similar to the above process, where epitaxial, lateral oxidation, and insulation protection processes are key processes.

FAB wafer processing

3) VCSEL Packaging

After VCSEL manufacturing, the entire wafer will undergo testing and dicing for shipment. VCSEL will be encapsulated on the module end, mainly for Die attach and wire bonding. The main purpose of Die attach is to establish conductive and thermal channels between VCSEL and module substrate. For VCSEL with different powers, different types of bonding epoxy resins are used to achieve different heat dissipation and reliability requirements.

After completing the substrate bonding, wire bonding will be performed. Generally, a single VCSEL emitting point can be bonded with a single wire. However, for high-power VCSEL arrays, multiple wire bonding is required to avoid high current fuse wires.

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