This letter describes the heteroepitaxy of InP on Si by MOCVD. A new epitaxial structure with a thin GaAs intermediate layer (InP/GaAs/Si) is proposed to alleviate the large lattice mismatch (8.4%) between InP and Si. Using this structure, a 4-inch InP single crystal with [...]
2019-08-19meta-author
PAM-XIAMEN, one of leading nanofabrication companies, has formed a compatible management system of multi-material, multi-user, multi-device, multi-process after years of exploration. The details as follows:
* Multi-Material
We can process multiple materials: Si, III-V semiconductor, glass, ceramic;
– Can process wafers of 6 inches and below, compatible [...]
2021-11-30meta-author
Silicon Nitride Waveguide – Substrates and Services Provided
PAM XIAMEN offers Silicon Nitride Waveguide
Clients fabricate SiN waveguides using contact lithography and pattern designs with waveguides with widths varying from 0.8 microns to 2.0 microns each of which has a straight reference waveguides and spiral waveguides [...]
2019-02-12meta-author
Precipitation in low temperature grown GaAs
The precipitation of arsenic in GaAs epitaxially grown at low temperature (LT GaAs) has been studied as a function of the post-growth annealing temperature by three independent methods: transmission electron microscopy (TEM), Raman scattering, and for the first time [...]
Highlights
•A recessed structure was used on the GaAs/Si solar cells to reduce the current path.
•The associated series resistance was reduced by a recessed structure.
•The carrier recombination loss was improved due to pyramid-like recessed structure.
In this study, epitaxial layers of GaAs-based solar cells were grown [...]
PAM-XIAMEN offers M Plane Si-GaN Freestanding GaN Substrate
Item
PAM-FS-GAN M-SI
Dimension
5 x 10 mm2 or 5 x 20 mm2
Thickness
380+/-50um
Orientation
M plane (1-100) off angle toward A-axis 0 ±0.5°
M plane (1-100) off angle toward C-axis -1 ±0.2°
Conduction Type
Semi-Insulating
Resistivity (300K)
>106 Ω·cm
TTV
≤ 10 µm
BOW
BOW ≤ 10 µm
Surface Roughness
Front side: Ra<0.2nm, epi-ready;
Back side: Fine Ground or polished.
Dislocation Density
≤ 5 x 10 6cm-2
Macro Defect Density
0 cm-2
Useable Area
> 90% (edge exclusion)
Package
each in single wafer container, under nitrogen atmosphere, packed in class 100 clean room
For more information, please contact us email at victorchan@powerwaywafer.com and powerwaymaterial@gmail.com
2020-08-20meta-author