Ceramic Substrate-1

PAM XIAMEN offers Aluminum Nitride Substrates: AlN.

AlN ceramic substrates are fabricated by tape casting technology. Its thermal conductivity is 4-5 times higher than Al2O3. It is an ideal substrate for
electronic thick and thin film applications.

                                                              Aluminum Nitride Ceramic Substrates Properties
Purity (wt%) 0.99 0.99 0.99 0.98 0.99
Density (g/cm3) 3.24 3.31 3.31 >3.25 >3.26
Thermal Conductivity (W/m. K) 140+/-10 >=170 180+/-10 100-300 >170
Thermal Expansion (x10-6/oC) < 5.6 4.4 < 5.6 <4.3 <4.2
Dielectric Strength (Kv/mm) >=25 >=15 >20 >15 >15
Dielectric Constant (at 1MHZ) 8.6 9 8.6 8.7 8.7
Loss Tangent (x104@1 MHz) 5 2 5 43531 43531
Volume Resistivity (ohm-cm) >1012 >1014 >5×1012 >1014 >1014
Flexural Strength (Kgf/mm2) 35.7 >35.7 > 30.6 >25 >30
Surface Roughness (micron) in Ra   as polished: 0.05 um or 2 microinch in Ra as polished: 0.1 um or 4 microinch in Ra as fired: 0.3 
as lapped: 0.075 
as polished: 0.025
as fired: 0.3 
as lapped: 0.075 
as polished: 0.025

AlN Ceramic Substrate 1″x1″x 0.5mm, 1SP
AlN Ceramic Substrate 10x10x 0.5mm, 1SP
AlN Ceramic Substrate 114.3mm x114.3mm x 0.5mm, as lapped on both sides
AlN Ceramic Substrate 2″x2″x 0.5mm, 2SP
AlN Ceramic Substrate 2″x2″x 1.0 mm, as lapping
AlN Ceramic Substrate 2″x2″x0.254mm, as lapped, 5 sheets/pack
0.04” Thick Graphite Substrate for RTP Furnace’s Sample Holder, 3” or 5” O.D Selectable – EQ-G-Holder
3” Dia x 0.025” Thick Aluminum Nitride Substrate for RTP Furnace’s Sample Holder – EQ-AIN-Holder

For more information, please visit our website: https://www.powerwaywafer.com,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Found in 1990, Xiamen Powerway Advanced Material Co., Ltd (PAM-XIAMEN) is a leading manufacturer of semiconductor material in China. PAM-XIAMEN develops advanced crystal growth and epitaxy technologies, manufacturing processes, engineered substrates and semiconductor devices. PAM-XIAMEN’s technologies enable higher performance and lower cost manufacturing of semiconductor wafer.

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