Silicon epitaxy with Boron dopant in size 200mm from PAM-XIAMEN is available for semiconductor device fabrication. Silicon epitaxy growth is a surface treatment process for silicon wafers, which means that a single crystal film is superimposed on the polished wafer by chemical reaction or other means, and the film layer is the silicon epitaxial layer. To know more details about the 200mm silicon based epitaxy, please refer to the table listed.
1. Parameters of Silicon Epitaxial Wafer
PAM210531-SIEPI
| 200mm Epitaxial Silicon Wafer | |||||
| ltem | Units | Limits | Test Method | Comments | |
| 1 Crystal/Bulk Characteristics | |||||
| 1.1 | Growth Method | – | – | – | CZ |
| 1.2 | Orientation | – | (100) | – | – |
| 1.3 | Dopant | – | Boron | – | – |
| 1.4 | Resistivity | Ohm*cm | 0.01-0.02 | – | – |
| 1.5 | Radial Resistivity Variation | % | Max 10% | ASTM F81 plan B | |
| 1.6 | Oxygen Concentration | ppma | 10-16 | New ASTM(F121-83) K=2.45 | |
| 1.7 | Radial Oxygen Variation | % | ≤10% | – | – |
| 1.8 | Bulk Metals Concentration, Fe | At/cm3 | NA | – | Cu/Fe/Ni/Al/Zn |
| 1.9 | Carbon Concentration | At/cm3 | Max 2.0*1016 | – | – |
| 1.10 | Dislocations | – | None | – | After Etching |
| 1.11 | Slip,Lineage,Twin,Swirl,Shallow Pits | – | – | ||
| 2 Polished Wafer/Substrate | |||||
| 2.1 | Surface Orientation | Degree | (100)±0.5 | – | – |
| 2.2 | Diameter | mm | 200±0.2 | – | – |
| 2.3 | Thickness | mm | 725±20 | – | – |
| 2.4 | Primary Flat Length | mm | Notched | – | SEMI M1.9-0699 |
| 2.5 | Primary Flat Orientation | Degree | {100} | – | – |
| 2.6 | Edge Profi (angle) | – | SEMI | – | – |
| 2.7 | Front surface visual inspection characteristics specified according to SEMI M1-0200 Table 1 | ||||
| 2.8 | Back Side Surface
Poly+ LTO(SiO2) |
Poly
8000±800+LTO8000±800A LTO outer |
– | – | |
| 2.9 | Edge exclusion (LTO)
-back side -front side |
mm | 0.5~2.0
None |
– | – |
| 2.10 | Back surface visual inspection characteristics specified according to SEMI M1-0200 Table 1 | ||||
| 3Epitaxial Wafer/Layer | |||||
| 3.1 | Surface Metals | At/cm-2 | ≤5E10 | – | Cu/Fe/Ni/Al/Zn |
| 3.2 | Bow/Warp | μm | ≤50 | – | – |
| 3.3 | Total Thickness Variation (TTV) | μm | ≤4 | – | – |
| 3.4 | Site Flatness (SFQR) | μm | ≤1 | – | 20*20mm, 100%
PUA |
| 3.5 | Dopant | – | Boron | – | – |
| 3.6 | Thickness Target Range | mm | According to epi code for attachment | ||
| 3.7 | Thickness Tolerance, w/w | % | ＜5 | Center(1pt) 10mm from edge(4 pts @ 90 degrees)
[Tmax-Tmin]÷[Tmax+Tmin]*100% |
|
| 3.8 | Resistivity Range | Ohm*cm | According to epi code for attachment | ||
| 3.9 | Resistivity Tolerance,w/w | % | ＜5 | Center(1pt) 10mm from edge(4 pts @ 90 degrees)
[Rmax-Rmin]÷[Rmax+Rmin]*100% |
|
| 3.10 | Edge Crown | – | NA | Projection above wafer surface not to exceed 1/3 of epi layer thickness | |
| 3.11 | Stacking Faults | cm-2 | ≤0.1 | ASTM F1810 | – |
| 3.12 | Etch Pit Density | cm-2 | ≤5 | – | – |
| 3.13 | Slip Line | – | SEMI M2-0997 | ASTM F523, SEMI M17 | – |
| 3.14 | Scratches,Dimples,Orange Peels,
Cracks/Fractures,Crow’s Feet,Haze, Foreign Matter |
– | None | ASTMF523 | – |
| 3.15 | Edge Chips | – | None | ASTMF523 | |
| 3.16 | Light Point Defect (Protrusion,Intrusion,
Spike, etc) |
EA
μm |
None | ASTMF523 | Laser automatic surface inspection |
| 3.17 | Nominal Edge Exclusion | mm | 3 | For items 3.2~3.4, 3.11~3.14, 3.16 | |
| Front surface visual inspection characteristics specified according to SEMI Table 5 SEMI M11-0200 | |||||
| 4.1 | Lazer marking on back surface hard, opposite to notch, SEMI M12 | ||||
| Back surface visual inspection characteristics specified according to SEMI Table 5 SEMI M11-0200 | |||||
Attachment for Technical Specification Epi
| Resistivity Range Ohm*cm | Thickness Range mm | ||
| 1 | MM6Bp 12.0_15.0 | 12±10% | 15±5% |
2. Silicon Epitaxy Process
The technology for epitaxy in silicon was developed in the 1960s, and it has mainly developed into three methods: gas phase epitaxy, liquid phase epitaxy, and silicon wafer molecular beam epitaxy. Among them, liquid phase epitaxy and molecular beam epitaxy are basically only used in laboratories due to high costs. The most important silicon epitaxy technology in the world is vapor phase epitaxy.
The principle of vapor phase epitaxy is to use some intermediate gases, such as silicon tetrachloride (SiCl4), silicon tetrahydrogen (SiH4), silicon trichlorosilane (SiHCL3), etc., to generate silicon atoms in the silicon epitaxial growth reactors and deposit the silicon atoms on the a monocrystalline silicon substrate.
Take the silicon tetrachloride hydrogen reduction reaction as an example. The silicon tetrachloride gas reacts with hydrogen at a high temperature of 1200°C (the chemical equation is: SiCl4 + 2H2 = Si + 4HCl) to generate Si silicon atom solid and reaction by-product HCl gas. At the same time, silicon atoms settle on the substrate to form a epitaxial layer.
3. Better Performance of Epitaxial Silicon Wafer Production
The epitaxial technology was first invented to solve the contradiction between high-frequency and high-power devices not only reducing resistance, but also requiring materials to withstand high voltages and high currents (high resistance). Through epitaxy, a high-resistance silicon wafer epitaxial layer can be grown on a low-resistance substrate, so that devices fabricated on the silicon epitaxial structures can simultaneously obtain high collector voltage and low collector resistance.
4. Silicon Epitaxy Advantages
In addition to the original design purpose, epitaxial technology also has the following significant advantages:
4.1 Perfect Epitaxy Silicon Surface
The epitaxial layer can improve the purity and uniformity of the material on the silicon epitaxy surface. Compared with mechanically polished wafers, the epitaxially processed silicon wafers have higher surface flatness, higher cleanliness, fewer micro-defects, and less surface impurities, so the resistivity is more uniform. It’s more easier to control surface particles, stacking faults, dislocations, silicon epitaxial layers defects, etc. Silicon epitaxy not only improves the performance of the epitaxial silicon detector, but also ensures the stability and reliability of the product.
4.2 Structure layering
Epitaxy can superimpose an epitaxial layer with different resistivity, doping elements, and silicon epitaxy doping concentration on the original substrate, which is the necessary process for semiconductor transistor manufacturing HBT (heterojunction bipolar transistor), MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). At the same time, since epitaxy provides different structural layers (different resistance on different layer), epitaxy is also one of the most common methods to solve the most common latch-up effect and short channel effect of CMOS technology.
4.3 Retro-doping
Doping refers to the process of deliberately introducing impurities into pure and impurity-free materials (intrinsic semiconductors) in the semiconductor manufacturing process to change the electrical properties of the materials. Doping can be divided into heavy doping, light doping, and medium doping according to the amount of doped elements. Under normal circumstances, the heavy doping must be above the light doping. Through the epitaxial silicon process, the interchange of doped structural layers or the combination of multiple dopings can be realized, which improves the flexibility and performance of device design on silicon epitaxy.
For more information, please contact us email at victorchan@powerwaywafer.com and powerwaymaterial@gmail.com.