The crystallinity of epitaxial graphene (EG) grown on a Hexagonal-SiC substrate is found to be enhanced greatly by capping the substrate with a molybdenum plate (Mo-plate) during vacuum annealing. The crystallinity enhancement of EG layer grown with Mo-plate capping is confirmed by the significant change of measured Raman spectra, compared to the spectra for no capping. Mo-plate capping is considered to induce heat accumulation on SiC surface by thermal radiation mirroring and raise Si partial pressure near surface by confining the sublimated Si atoms between SiC substrate and Mo-plate, which would be the essential contributors of crystallinity enhancement.
Graphene is a 2D material composed of a monolayer of carbon atoms arranged in a honeycomb lattice structure1,2,3,4. Owing to its superior electron and hole mobilities, graphene has been considered to be a promising candidate material for ultra-fast electronic devices operating in THz frequency regime5. The first successful isolation of graphene was achieved by mechanically exfoliating highly oriented pyrolytic graphite (HOPG)2. Although high-quality single crystal graphene flakes can be obtained by mechanical exfoliation, the sizes of graphene flakes are too small (<100 μm) for practical applications6. Several alternatives including chemical vapor deposition (CVD)7,8, solid source deposition9,10, and surface graphitation of SiC4,6,11,12,13,14 have been explored for the synthesis of large-scale graphene. Of particular interest is the surface graphitation of a single crystalline SiC by thermal annealing in ultra high vacuum (UHV)4 or Ar environment6 at high temperature (>1300°C). In this process, only Si atoms are sublimated from the surface and the remaining C atoms rearrange to form a sample-size uniform so-called epitaxial graphene (EG) either on Si-face (0001) or C-face (000-1) surface15. The EG grown on C-face surface is normally thicker (typically 10–20 layers) than that on Si-face surface but its carrier mobility can reach as high as 18,700 cm2V−1s−1 14. Hass et al.showed from first-principles calculations that such high carrier mobility of C-face EG is due to the unique rotational stacking faults residing in C-face EG16. These rotational stacking faults decouple the adjacent graphene layers electronically and make the multiple graphene layers maintain the electronic properties of an isolated single layer graphene. Very recently, Trabelsi et al. have reported that a few or even single layer of graphene could be grown epitaxially on C-face surface in the form of islands (hundreds of μm) or freestanding bubbles (several μm)17,
18. Their results imply that it is possible to control the thickness of EG grown on C-face surface by carefully adjusting the Si flux supplied externally and the growth time during the conventional UHV annealing. Based on the large-scale availability and good electrical properties, the EG on SiC surface (either Si-face or C-face) clearly demonstrates the potential to be used as a platform for future electronic devices. However, it is necessary to work continuously on lowering the formation temperature of EG while maintaining its superior electrical properties in order to fabricate high-performance electronic devices at reduced processing costs. This is quite crucial for the actual commercialization of EG-based electronics in competition with the current Si technology. In this work, we have developed an experimental method to significantly improve the crystallinity of EG grown on a Hexagonal-SiC substrate simply by capping the substrate with a molybdenum plate (Mo-plate) during UHV annealing.
Growth of EG films on n-type C-face 4H-SiC surface with Mo-plate capping and structural analyses
The EG film was first grown on an n-type C-face 4H-SiC substrate 4-degree miscut to <11–20>. The SiC substrate was chemically cleaned with HF (49%) for 1 min followed by methanol rinse to remove native oxides. The Mo-plate was also cleaned with HCl:H2O (2:1) solution for 10 min followed by DI rinse and annealing at 500°C in UHV to remove the residues from machining processes. In order to compare the growth of EG with and without Mo-plate capping, the C-face surface of one 4H-SiC sample was in contact with the Mo-plate while that of the other 4H-SiC sample was exposed to UHV environment during annealing as shown in Figure 1. The samples prepared this way were annealed for 10–60 min at 850–950°C, which is substantially lower than the conventional vacuum annealing process. The temperature was measured by using both an IR pyrometer and a thermocouple for cross-checking. The chamber base pressure was 6.0 × 10−9 Torr and the working pressure became as high as ~4.6 × 10−6 Torr when the annealing time reached 60 min at 900°C.