MOS SiO2/GaN structures were fabricated with different surface preparation and different PECVD processes for the dielectric thin film deposition (ECR-PECVD and ICP-PECVD in continuous and pulsed modes). On the basis of C-V curves, the surface preparation steps, involving chemical etching with BOE, UV-Ozone oxidation and oxygen plasma oxidation, were compared in terms of resulting effective charge and interface trap density. A good SiO2/GaN interface quality was achieved for N-type MOS capacitances obtained both with continuous‑ICP‑PECVD and ECR-PECVD deposition of the SiO2 dielectric. However, the interface quality is greatly reduced for MOS capacitors fabricated on P-type GaN.
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