GaN on Si for Power, E-mode

GaN on Si for Power, E-mode

PAM-XIAMEN offers GaN on silicon HEMT wafer for Power, E-mode. Because the normally-on characteristic will Increase the complexity of circuit design and power consumption, designing an enhanced (E-Mode) HEMT that is turned off under zero grid bias will be crucial for advancing the application of GaN-on-Silicon HEMT in the power field.

1. Structure of E-MODE GaN HEMT on Silicon Substrate

GaN on silicon HEMT epitaxy size2″, 4″, 6″,8″
AlGaN/GaN HEMT structureRefer 1.2
Residual 2DEG density (Vg=0 V)<1e18/cm3
AFM RMS (nm)of 5x5um2<0.25nm
Edge exclusion <5mm
u-GaN cap layer /
Al composition20-30%
AlGaN barrier layer /
GaN channel/
AlGaN buffer/
Substrate materialSilicon substrate
Si wafer thickness (μm)675um(2″), 1000um(4″), 1300um(6″), 1500um(8″)


2. What is E Mode GaN on Silicon HEMT?

Changing the process structure of the GaN on silicon HEMT gate to switch the threshold voltage polarity can produce an enhanced (E-type) GaN HEMT device. The purpose of the process structure change is to deplete the 2DEG under the gate with the condition of no applied voltage, so that the forward threshold voltage can be enhanced by the 2DEG to form a channel. P-doped GaN gate is a structure similar to a diode in the gate structure, and the threshold voltage is raised by the diode voltage drop.

Currently, there are three main methods for using p-type gate to realize GaN-based enhanced mode HEMT:

  • The first method of p-type gate is mainly to use the entire epitaxial p-type layer on the barrier layer, and then etch and retain the p-type layer under the gate to realize the enhancement;
  • The second is to trim the p-type epitaxial layer, then retain the p-type layer under the gate, and etch most of the p-type layer in the non-gate area, leaving 5-20 nanometers of the p-type layer. During the etching process, plasma will damage the interface and affect the stability of the GaN on silicon power device;
  • The third method of p-type gate is to do secondary epitaxy in the gate area on the barrier layer to grow the p-type gate.

For more information, please contact us email at [email protected] and [email protected].

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