Geometry and Thermal Stress Analysis of In-plane Outgassing Channels in Al2O3-Intermediated InP (Die)-to-Si (Wafer) Bonding

  • Home
  • News
  • Geometry and Thermal Stress Analysis of In-plane Outgassing Channels in Al2O3-Intermediated InP (Die)-to-Si (Wafer) Bonding

Geometry and Thermal Stress Analysis of In-plane Outgassing Channels in Al2O3-Intermediated InP (Die)-to-Si (Wafer) Bonding

Thermal-mechanical characteristics and outgassing efficiency of integrated in-plane outgassing channels (IPOCs) at Al2O3-intermediated InP (die)-to-Si (wafer) bonding interface is investigated. The IPOCs are introduced and investigated via both multi-physics simulation and experimental demonstration. Thermal stress simulation indicates that Al2O3 bonding layer efficiently mitigates the stress as observed at top InP surface, compared to that of conventional SiO2 intermediate layer. By introducing IPOCs, the thermal stress decreases with increasing IPOC spacing-to-width (S/W) ratio. Experimentally, high quality InP/Al2O3/Si direct bonding is firstly demonstrated. Seamless bonding interface is observed, along with reasonable bond shear strength of 2.57 MPa and minimal residual stress in the transferred InP layer. Efficiency of the IPOCs is then evaluated by comparing interfacial void densities of InP bonded on dimension-varied-IPOC-patterned Si. A significant void density reduction up to two orders of magnitude is observed, with a decreasing S/W ratio. An optimal S/W ratio of 2.5 is therefore proposed to compromise between the thermal stress degradation (~10%) and outgassing efficiency improvement (~90% void density suppression). This work is thus significant as it could provide guidelines to establish high quality hybrid-integrated optoelectronic devices for Si photonic applications.

Source:IOPscience

For more information, please visit our website: https://www.powerwaywafer.com,
send us email at [email protected] and [email protected]

2020-03-09

Share this post

Related Posts

Electrolytic Removal of P‐Type GaAs Substrates from Thin, N‐Type Semiconductor Layers

An electrolytic etching technique has been developed which can remove p‐type GaAs substrates from thin (2–10µ) n‐type layers of  or . Sodium hydroxide is used as the electrolyte, and is sprayed continually over the etching surface to prevent the build‐up of “flakes” on the p‐type surface [...]

2019-12-23meta-author
3″ Silicon Wafer-1

PAM XIAMEN offers 3″ Silicon Wafer. Diameter Type Dopant Growth method Orientation Resistivity  Thickness Surface Grade 76.2 N Phos CZ -100 1-20 43768 P/P PRIME 76.2 N Phos CZ -100 1-20 40-60 P/P PRIME 76.2 N Phos CZ -100 1-20 80-100 P/P PRIME 76.2 N Phos CZ -100 1-20 140-160 P/P PRIME 76.2 N Phos FZ -100 >3000 300-350 P/P PRIME 76.2 N Phos CZ -100 1-20 300-350 P/P PRIME 76.2 N Phos CZ -100 1-20 300-350 P/E PRIME 76.2 N Phos CZ -100 350-400 P/E/OX PRIME 76.2 N As CZ -100 .001-.005 350-400 P/E PRIME 76.2 N Sb CZ -100 .005-.02 350-400 P/E PRIME 76.2 N Phos FZ -100 >3000 350-400 P/E PRIME 76.2 N Phos CZ -100 1-20 350-400 P/E PRIME 76.2 N Phos CZ -100 1-20 350-400 P/E/DTOx PRIME 76.2 N Phos CZ -100 1-20 350-400 P/E/Ni PRIME 76.2 N Phos CZ -100 1-20 350-400 P/E/WTOx 76.2 N Phos CZ -100 20-50 350-400 P/P PRIME 76.2 N Phos CZ -100 20-50 350-400 P/P PRIME 76.2 N Phos CZ -100 20-50 400-450 P/E PRIME 76.2 N Phos CZ -100 450-500 P/P PRIME 76.2 N Phos CZ -100 500-550 P/E PRIME 76.2 N Phos CZ -100 950-1000 P/P PRIME For more information, please visit our website: https://www.powerwaywafer.com, send us email at [email protected] and [email protected] Found in 1990, Xiamen Powerway Advanced Material Co., Ltd (PAM-XIAMEN) is a leading manufacturer of semiconductor material in China.PAM-XIAMEN develops advanced crystal growth and epitaxy technologies, [...]

2019-03-04meta-author
Nickel Substrate & Foil-1

PAM XIAMEN offers Nickel Single crystal. tomic number:  28  Atomic number:  28  Atomic mass:     58.71 g.mol -1 Atomic mass:     58.71 g.mol -1 Crystal structure:  F.C.C Crystal structure:  F.C.C Lattice Constant:         0.325 nm  Lattice Constant:         0.325 nm    Ni Single crystal Ni Single Crystal Substrate, <100>, 10 x 5 x 0.5 mm, 1 side polished Ni Single Crystal Substrate, <100>, 10×10 x [...]

2019-05-13meta-author
Single crystal SrLaGaO4

PAM XIAMEN offers Single crystal SrLaGaO4. Single crystal SrLaGaO4, (100), 10×9.8×0.5mm 1sp Single crystal SrLaGaO4, (001), 10x3x0.5mm , one side polished Single crystal SrLaGaO4, (001), 10x5x0.5mm , one side polished Single crystal SrLaGaO4, (100), 10x10x0.5mm 2sp Single crystal SrLaGaO4, (100), 10x3x0.5mm , one side [...]

2019-05-14meta-author
Study of Highly Pixelated CdZnTe Detector for PET Applications

Study of Highly Pixelated CdZnTe Detector for PET Applications We are investigating the feasibility of a high-resolution PET insert device based on a Cadmium Zinc Telluride (CdZnTe) detector with 350 μm anode pixel pitch to be integrated into a conventional animal PET scanner to improve its [...]

2013-10-23meta-author , ,
GaAs/AlGaAs/GaAs epi wafer

GaAs / AlGaAs / GaAs epi wafer in the diameter of 2” or 4” is available. This GaAs epitaxial wafer is applicable for semiconductor microwave devices and microwave monolithic integrated circuits. Here comes the typical structure of gallium arsenide epi wafer, please see below: 1. GaAs Wafer Epitaxial Structures Structure 1: 2”GaAs/AlGaAs/GaAs epi wafer S.No Parameters Specifications 1 GaAs substrate layer [...]

2013-11-19meta-author