How Does Semiconductor Wafer Technology?

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The development of silicon wafer can be attributed to the development of Moore’s law. Because the silicon wafer for semiconductor is round, so the semiconductor silicon wafer is also called “silicon wafer” or “wafer”. Wafer is the “substrate” of chip manufacturing. All chips are manufactured on this “substrate”. After manufacturing, the substrate is cut into a single chip, and then packaging test is carried out. In the development of semiconductor silicon wafers, they are developed in two directions: size and structure.

In terms of size, the development path of silicon wafer is from small to large; in the early stage of integrated circuit development, 0.75 inch wafer is used. Later, in order to reduce the cost of a single chip, increasing the wafer area and increasing the number of chips on a single wafer. Around 1965, with the development of Moore’s law, integrated circuit technology and silicon chip ushered in a period of rapid development. Silicon wafer manufacturing technology is becoming more and more advanced, and gradually developed to 4-inch, 6-inch, 8-inch and 12 inch wafers. In 2001, Intel and IBM jointly developed a 12 inch wafer manufacturing line. At present, 12 inch wafers are the main part of the world’s semiconductor wafers, accounting for about 70%, and will be developed to 18 inch (450mm) wafers in the future.

In terms of structure, the development path of silicon wafer is from simple to complex; at the beginning of the development of integrated circuit, there is only one use of logic chip, but later the application scenarios are expanding, such as logic chip, power device, analog chip, mixed digital and analog chip, flash / DRAM memory chip, RF chip, etc. Different application scenarios lead to different forms of silicon chips in structure.

PW (Polish wafer):

it is a commonly used polishing wafer. After pulling the single crystal to get the ingot, the directly cut silicon wafer has some defects in smoothness or warpage, so it is first polished. This is also the most primitive way of processing silicon.

AW(Anneal wafer):

with the continuous development of the process technology, the process linewidth is shrinking, and the defects of polished wafer are exposed, such as local atomic lattice defects on the wafer surface due to polishing, high oxygen content on the wafer surface, etc. In order to solve this problem, the annealed wafer was developed. After polishing, the silicon wafer was placed in an inert gas filled furnace tube (usually argon) for high temperature annealing. In this way, the lattice defects on the surface of silicon wafer caused by polishing can be repaired, and the oxygen content on the surface of silicon can also be reduced.

EW(Epitaxy wafer):

with the increasing application scenarios of integrated circuits, the standard silicon wafers manufactured by the silicon factory can no longer meet the requirements of some products in terms of electrical characteristics. At the same time, the lattice defects reduced by thermal annealing can not meet the needs of smaller and smaller linewidth. This leads to epitaxy wafers (or EPI wafers). The usual epitaxial layer is silicon film. Based on the original silicon wafer, a layer of silicon film is grown by using the thin film deposition technology. Because the silicon substrate exists as a seed crystal in silicon epitaxy, the new epitaxial layer will duplicate the crystal structure of silicon wafer. Because the substrate is a single crystal, so the epitaxial layer is also a single crystal. However, due to the lack of polishing, the lattice defects on the surface of the grown wafer can be minimized.

The emphasis of epitaxial technology includes the thickness and uniformity of epitaxial layer, the uniformity of resistivity, bulk metal control, particle control, stacking fault, dislocation and other defect control. By optimizing the reaction temperature of epitaxy, the velocity of epitaxial gas, the temperature gradient of center and edge, the company has achieved the optimal epitaxial layer quality. Due to the different products and the need of technology upgrading, the company continuously optimizes the epitaxial process to achieve the effective matching of the epitaxial layer thickness and the substrate geometry, and obtains the optimal flatness, the lowest metal impurities, the best thickness and resistivity uniformity of the epitaxial layer, so as to meet the requirements of different specifications of products.

In addition, the epitaxial wafers can generate epitaxial layers with different resistivity, doping elements and doping concentration from the original wafers, which makes it easier to control the electrical properties of the wafers. For example, a layer of n-type epitaxial layer can be formed on p-type silicon chip, thus forming a low concentration hybrid PN junction, which can optimize the breakdown voltage and reduce the latch up effect in the subsequent chip manufacturing. The thickness of the epitaxial layer is generally different according to the different use scenarios. Generally, the thickness of the logic chip is about 0.5 μ m to 5 μ m, and the thickness of the power device is about 50 μ m to 100 μ m due to the need to withstand high voltage.

SW (SOI wafer): the full name of SOI is silicon on insulator. Because SOI silicon has small parasitic capacitance, small short channel effect, high inherited density, fast speed and low power consumption, especially in the parameter of low substrate noise, SOI silicon is often used in RF front-end chip because of non SOI silicon. In the common polished silicon or epitaxial silicon, the noise current interference can not be solved. Because the IC is a four terminal device, it must be connected with voltage on the substrate, so it forms the current path between the chip and the substrate, which will generate noise current, thus affecting the characteristics of the IC. Especially in the field of RF chip, the switch speed is fast, and the noise current produced by substrate will seriously affect the switch performance. In order to solve the problem of substrate noise, SOI technology is invented.

For more information, send us email at victorchan@powerwaywafer.com and powerwaymaterial@gmail.com