(Invited) Strain Engineered Crack-Free GaN on Si for Integrated Vertical High Power GaN Devices with Si CMOS

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  • (Invited) Strain Engineered Crack-Free GaN on Si for Integrated Vertical High Power GaN Devices with Si CMOS

The ability to grow thin GaN layers on Si substrates has led to the development of lateral high power and high-speed devices such as GaN HEMTs. These devices have already demonstrated promising performance and have been adopted for mass market. But lateral devices require large drain/gate separation to sustain high voltage impairing cost effectiveness. This highlights the need for growth of thick GaN layers to enable vertical high power device architectures and to achieve high performance and attain high breakdown voltages in small chip area. This paper presents a successful growth of over 10μm thick crack-free GaN on Si by engineering the strain induced by thermal mismatch between GaN and Si. We discuss the origin of cracking and introduce a surface strain-relief mechanism in 0.5mm diameter GaN dots to overcome thermal mismatches. The first demonstration of vertical thick GaN Schottky diodes on Si will be presented. To fully exploit these results of GaN power devices on Si, side-by-side integration of GaN and CMOS circuitry elements is necessary. We have assessed and validated the compatibility of the GaN-CMOS process. These advances can pave the way for commercialization of next generation compact and efficient power systems that are composed of monolithically integrated GaN and Si technologies.

Source:IOPscience

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2020-01-20

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