Q: What is the minimum batch size for blue LED wafers on 4 inch sapphire (patterned sapphire)?
Q: What is the minimum batch size for blue LED wafers on 4 inch sapphire (patterned sapphire)? A:5pcs is ok, but the price would be higher.
Q: What is the minimum batch size for blue LED wafers on 4 inch sapphire (patterned sapphire)? A:5pcs is ok, but the price would be higher.
Q: What is the minimum batch size for blue LED wafers on 4 inch sapphire (patterned sapphire)? A:5pcs is ok, but the price would be higher.
Q: For blue wafer epi on flat substrate, it would be important to omit / leave out the u-GaN layer as we want to LLO and backside conacting. Is that possible? A:Yes, it is no problem, some clients bought our wafers for LLO.
Q:Do these 2” PSS LED wafers have the same epi-stack as the 4” PSS? If not, please send me the diagram with thicknesses. Wavelength can be same: central 455nm A: the 2″ detail layer thickness and structure is same as 4″, no any difference. Wavelength:455nm+/-5nm is no problem.
Q: I am not sure whether practically LLO can be done on the PSS given it is not a flat surface A: “laser lift-off” actually is according to “NL layer” as below image. If the NL layer is GaN layer, when it is heating to constant high temperature, the GaN is decomposed into [...]
Q:For 4” pss wafer, the light comes out from the p-GaN side not from sapphire, so I can’t do flip chip packaging. Also I don’t know whether laser liftoff is possible for pss wafer. Is it possible you can share any image of the etched surface of pss? A: 4″LED wafer on pps [...]
Q: Regarding blue LED epi wafer, after MOCVD, do you anneal the wafer for p-GaN activation? A:Yes!
Q: The epitaxial wafer on pss substrate is attractive to me, so I want to know the overall efficiency it can deliver. Could you please tell me an efficiency number (lm/w or cd/A or EQE) of the device based on a structure similar to the picture in your email? A:Please [...]
Q: Regarding LED epi wafer,does the price include fabrication of p and n metal contacts? If not, can you fabricate p and n contacts plus SiO2 passivation based on my design? This can turn to a bigger project. A: Sorry, we can not offer fabrication of p and n metal contacts, [...]
Q: What is the highest temperature and the highest thermal shock that the wafers can withstand? A: At the temperatures higher than 1000 C on the free surface of Si-face of 6H-SiC (0001) the carbon segregation properties are started so that during short time the thin carbon layer is appeared due [...]
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