Epitaxy Growth on C-Face 4H-SiC and Its Application in Schottky Diodes +

PAM-XIAMEN can grow 4H-SiC epitaxy for various diodes. Send your demands to [email protected], we will suggest you the most suitable wafers.

At present, most 4H-SiC devices are prepared based on silicon face (Si-face) substrates, and their epitaxial technology is relatively mature. However, in recent years, carbon face (C-face) 4H-SiC epitaxy has gradually attracted the attention of researchers due to its unique advantages in defect control, surface morphology, and interface properties.

Compared to the Si surface, the 4H-SiC epitaxial layer on the C surface has a higher conversion efficiency from basal plane dislocations to edge dislocations, which helps to reduce BPD density and improve the reliability of bipolar devices. In addition, C-plane epitaxy can achieve a smooth surface without step focusing under wider growth conditions, which is beneficial for reducing the leakage current of MOS devices. Saitoh et al. found that C-face MOSFETs have lower interface state density and higher channel mobility. Despite the difficulty of grinding the C-face substrate, high background doping concentration, and difficulty in controlling uniformity, its potential in device performance still deserves further exploration.

1. Epitaxial Growth and Morphology Control of 4H-SiC on C-Face Substrate

Zhao et al.’s research indicates that obtaining high-quality C-face epitaxial layers strongly relies on precise control of key growth parameters, including C/Si ratio, growth temperature, and hydrogen etching time.

1.1 Control of Surface Morphology by Growth Parameters

The C/Si ratio is the primary factor affecting the type and density of surface defects. Research has shown that under the condition of a C/Si ratio of 0.9, carrot like defects appear on the surface of the epitaxial layer; When the C/Si ratio is optimized to 1.2, a defect free mirror like surface can be obtained; When the C/Si ratio is further increased to 1.5, excess carbon will promote the formation of comet like defects. This indicates the existence of a narrow optimal C/Si ratio window to achieve defect free growth.

Fig. 1 Epitaxial morphology of 4H-SiC on the C-face under different C/Si ratios

The growth temperature directly affects the control of crystal polymorphs. At temperatures below 1550°C, the surface of the epitaxial layer maintains a mirror like state. However, when the temperature rose to 1575°C, defects in the 3C-SiC inclusions began to appear, which were attributed to pre-existing 3C crystal nuclei on the substrate surface or particle contamination in the reaction chamber. Therefore, moderate growth temperature is crucial for maintaining the crystal purity of 4H-SiC.

Fig. 2 Surface morphology of 4H-SiC epitaxial growth on C-plane at different growth temperatures

1.2 Hydrogen Etching and Defect Formation

The duration of hydrogen etching, as an in-situ pretreatment process before growth, has a critical impact on surface integrity. Short etching (such as 5 minutes) can lead to a unique triangular defect perpendicular to the off-axis direction. The shape of this defect is similar to an inverted pyramid, and its formation mechanism is due to the easy formation of C-C bonds on C-face in a carbon rich environment, which interrupts the normal step flow growth mode. On the contrary, excessive etching will exacerbate surface roughness and induce step focusing. Research has shown that an etching time of about 15 minutes is an equilibrium point for obtaining an ideal surface.

Fig. 3 Microscopic images of 4H-SiC epitaxial growth on the C surface at different etching times

Atomic force microscopy analysis shows that by optimizing the above parameters, an atomically flat surface can be obtained on the C-face, with a root mean square roughness (RMS) as low as 0.208nm (C/Si=1.2). Compared with Si-face, the surface roughness of C-face epitaxial layer is less sensitive to growth temperature and C/Si ratio fluctuations, indicating its potential to achieve smooth surfaces within a wider process window.

Fig. 4 AFM images of 4H-SiC epitaxial layers grown on (a) C surface and (b) Si surface under different growth conditions

2. Performance Verification of C-Face 4H-SiC Schottky

The high quality of materials is the foundation of high-performance devices. Roth et al. fabricated Schottky barrier diodes (SBDs) using high-quality C-face 4H SiC epitaxial materials and Ti/Al metal stacks, and thoroughly characterized their electrical properties.

2.1 Ideal Schottky Contact Characteristics

The observation of Ti/Al metal semiconductor interface by transmission electron microscopy (TEM) further reveals that the contact interface presents an atomically smooth state without obvious interface reaction layer, which provides a guarantee for the formation of ideal Schottky contact.

Fig. 5 TEM image of Ti/Al metal semiconductor interface

The Schottky barrier height (ΦB) extracted through current voltage (I-V) testing is approximately 1.20eV, and exhibits good uniformity among different devices (distributed between 1.15-1.22eV). This value was further validated through the Arrhenius plot. The capacitance voltage (C-V) test shows that the doping concentration of the epitaxial layer is uniform, about 9.6 × 10¹⁵cm^-3.

Fig. 6 Electrical properties of C-face 4H-SiC Schottky barrier diode: (a) Linear I-V, (b) Log (I) – V, (c) Arrhenius plot

2.2 Excellent High Temperature Characteristics and Switching Performance

The temperature dependent I-V measurement reveals the excellent performance of C-plane epitaxial Schottky diodes. At temperatures up to 200°C, the reverse leakage current of the device is still suppressed at <6pA, at an extremely low level, demonstrating its excellent high-temperature stability.

More importantly, its forward conduction characteristics exhibit unique temperature dependence: when the forward current is below 1μA, the forward voltage decreases with increasing temperature; When the current is higher than 1μA, the forward voltage increases with temperature. This behavior helps to reduce the reverse recovery time of the diode, thereby significantly improving the switching speed of the device, which is crucial for high-frequency power applications.

In summary, by regulating the C/Si ratio, growth temperature, and hydrogen etching time, high-quality, atomically flat C-face 4H-SiC epitaxial growth can be achieved. The Schottky barrier diode prepared based on C-face 4H-SiC epitaxial wafer exhibits high barrier height, excellent high-temperature blocking characteristics, and unique switching performance, fully demonstrating the application value of C-face epitaxy in high-efficiency and high reliability power diodes.

Whether you need 4H-SiC epitaxial wafer for research or for industrial applications, please contact us email at [email protected] and [email protected].

 

References:

1. Zhao, Z., Li, Y., Xia, X., Wang, Y., Zhou, P., & Li, Z. (2020). Growth of high-quality 4H-SiC epitaxial layers on 4 off-axis C-face 4H-SiC substrates. Journal of Crystal Growth, 531, 125355.
2. Voo, Q. G. R., Yeo, A. H., Bera, L. K., Chand, U., Chien, Y. C., Nguyen, X. S., … & Boudin, L. (2025, October). C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes. In Materials Science Forum (Vol. 1159, pp. 9-13). Trans Tech Publications Ltd.