4 인치 SiC Epi 웨이퍼

4 인치 SiC Epi 웨이퍼

As one of leading SiC epi wafer suppliers, PAM-XIAMEN offers SiC epi wafer, and the SiC epi wafers type includes N type and P type. The SiC epi wafer thickness from 1um to 250um can be produced, and the silicon carbide epi wafer prices are competitive. What is SiC epi wafer? SiC epitaxial wafer is an intermediate link in the core of the SiC industry chain. At present, a whole set of industrial systems from silicon carbide substrates and SiC epi wafers to device preparation have been formed in the world. In the epi wafer market, high-quality SiC epitaxy are the basic materials of SiC power devices. The current development trend of silicon carbide epitaxial materials required by power electronic devices at home and abroad is developing in large diameter, low defects, high uniformity and etc.

SiC Epi 웨이퍼

 

1. 4 인치 SiC Epi Wafer 사양

항목 1 :
PAM201221-SIC-EPI

의 SiC 기판
직경 100mm
두께 350um
폴리 타입 4H-SiC를
전도도 N 형
대한 오프 오리엔테이션 4도 비축
MPD ≤1 / cm2
저항 0.015 ~ 0.028 옴 -cm
표면 마무리 닦는 양면
에피 층
완충기:
두께 0.5um, n 형
도핑 수준 1E18cm3
에피 1 :
두께 6um +/- 5 %
n- 도핑 수준 5.2E15 / cm3

 

항목 2 :
PAM210514-SIC-EPI

의 SiC 기판
직경 100mm
두께 350um
폴리 타입 4H-SiC를
전도도 N 형
대한 오프 오리엔테이션 4도 비축
MPD ≤1 / cm2
저항 0.015 ~ 0.028 옴 -cm
표면 마무리 닦는 양면
에피 층 :
완충기:
두께 0.5um, n 형
도핑 수준 1E18cm3
에피 1 :
두께 6um +/- 5 %
n- 도핑 수준 <1E15 / cm3
낮은 O, B, P 및 Al 원소 : B <0.06PPM; P <0.05PPM; Al <0.01PPM; O없이

 

2. SiC Epi in the Fields of Low Voltage, Medium Voltage and High voltage

적용 측면에서 우리는 일반적으로 실리콘 카바이드를 저전압, 중전 압 및 고전압의 세 영역으로 나눕니다. 저전압의 경우 주로 PFC 및 전원 공급 장치와 같은 일부 가전 제품에 사용됩니다. 중전 압은 주로 자동차 전자 제품에 사용되며 중전 압은 향후 SiC 에피 웨이퍼 개발을위한 주요 응용 방향이기도합니다. 세 번째는 철도 운송 및 3300V 이상의 전력망 시스템과 같이 상대적으로 높은 전압 레벨을 가진 애플리케이션 끝입니다.

동시에, 우리는 실리콘 카바이드와 갈륨 질화물이 여전히 중전 압 및 저전압 분야에서 경쟁 관계에 있음을 알 수 있지만 고전압 분야에서는 재료 성숙도 관점에서 볼 때 실리콘 카바이드는 고유 한 이점이 있습니다 . 그러나 지금까지 고전압 분야에서 성숙한 제품이 없었던 것은 유감입니다. 고전압 분야 용 SiC 에피 웨이퍼는 전 세계적으로 연구 개발 단계에 있지만 중저 전압 실리콘 카바이드 에피 택셜 웨이퍼는 이미 시장에서 다이오드 및 MOSFET 제품에 적용되고 있습니다.

3. 100mm 4H SiC Epitaxial Wafer Norm

This norm applies to 4H silicon carbide (4H-SiC) epitaxial wafers. The SiC wafer production is mainly used to manufacture power semiconductor devices or power electronic devices.

3.1 Requirements of 4H-SiC Epitaxial Growth in 4 Inch

The substrate is a (0001) silicon surface 4H-SiC wafer with an angle of 4° in the <11-20> direction. The ratio of 4H crystal type to the total area of the silicon carbide wafer should not be less than 90%. The surface of the wafer can be polished on one side or on both sides. The silicon surface of the wafer should be chemically mechanically polished with a surface roughness of less than 0.5 nm. The number of cleanable particles on the surface of the wafer (diameter ≥0.5 um) does not exceed 15/piece.

3.2 Epitaxial Quality Requirements for the SiC wafer

Surface defects of SiC epitaxy should meet the requirements of the following table.

Maximum Allowable Limit
Industrial Grade Research Grade
Carrots ≤80pcs/wafer ≤100pcs/wafer
Comets
Triangles
Downfalls
Edge Removal 3 mm 3 mm

 

The surface roughness of SiC wafer in size of 4” should be less than 5.0 nm in the entire 4H-SiC epitaxial wafer range.

The thickness uniformity of the 4-inch SiC epitaxial layer should meet: industrial grade ≤5% and research grade ≤7%

Doping concentration uniformity for industrial grade should be ≤30%, and that for research grade should be ≤35%.

4. FAQ about SiC Epitaxy

질문 1: I looked at the SiC homoepitaxial wafers on your company website before, and they all have buffer layer. I would like to ask what is the function of the intermediate buffer layer? What effect will it have on the epitaxial layer if directly epitaxial without a buffer layer?

: The role of the intermediate buffer layer in SiC homoepitaxy is to reduce defect density and provide epitaxial yield.

질문 2: Is there a big difference between the growth temperature of the buffer layer and the epitaxial layer of 4H-SiC epitaxial wafer?

: There is little difference in growth temperature for buffer and epitaxial layer of 4H-SiC epi wafer.

질문 3: I am interested in your standard Instrinsic SiC on 4H SiC substrate.The application is to produce electrochemically suspended membranes of ui doped SiC from a n-type substrate, hopefully of thicknesses between 500nm-2000nm. We are trying to determine the performance of our electrochemical undercut process on Si-face and C-face material. Does high wafer resistivity come from high compensation by deep levels, or from a low concentration of impurities in the epi-layer?

: If so, I think you need 500nm undoped SiC on n-type SiC substrate. Suggest you use thicker thickness. If you must require 2um, we also can do it, the carrier concentration of undoped SiC should be <1E5, typical ~1E4.

Q4: Is it possible to have 4H-SiC epitaxial on 3C-SiC with 20-40micron thickness?

: 4H-N SiC on 3C-N SiC is prone to phase transition and is not easy to control. Generally speaking, under epitaxial conditions, it is easier to form 3C crystal forms, so it is difficult to estimate the difficulty of epitaxial 4H on 3C. But we can supply 350um thick freestanding 3C-SiC substrate, more specifications please refer to https://www.powerwaywafer.com/3c-sic-wafer.html.

 

SiC epi 웨이퍼에 대한 자세한 내용은 다음을 참조하십시오.

4H 150mm의 n 형의 SiC 웨이퍼 EPI

4H SiC 에피 택셜 웨이퍼

실리콘 카바이드 에피 택셜 웨이퍼가 필요한 이유는 무엇입니까?

자세한 내용은 다음 주소로 이메일을 보내주십시오. victorchan@powerwaywafer.compowerwaymaterial@gmail.com.

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