Atomic Layer Deposition (ALD), also known as atomic layer epitaxy (ALE), is an atomic-scale thin film preparation technology. It can deposit ultra-thin films with uniform thickness, controllable thickness and adjustable composition. With the development of nanotechnology and semiconductor microelectronics, the size requirements of devices [...]
2022-05-31meta-author
SiC epitaxial wafer is available for fabricating MOSFET devices, wafer specifications can be found in https://www.powerwaywafer.com/sic-mosfet-structure.html
1. Epitaxial Pits
Epitaxial pits, as one of the most common surface morphology defects, have a typical surface morphology and structural profile as shown in Fig.1. The position of thread [...]
2024-03-21meta-author
VCSEL Market Overview
At present, the world’s major designers include Finsar, Lumentum, Princeton Optronics, Heptagon, IIVI and other companies, which are at the forefront of R&D roles on the mobile VCSEL. III-V EPI epitaxial wafers are supplied by companies such as IQE, PAM-XIAMEN, VPEC and Landmark [...]
2018-09-27meta-author
PAM-XIAMEN offers 2inch or 4inch red infrared AlGaAs / GaAs LED epi wafer with wavelength 850-880 nm and 890-910nm:
1. Red Infrared AlGaAs / GaAs LED Epi Wafer
PAM-190723-LED
Structure
Thickness, um
Type
Composition
CC, cm-3
Wide-gap window
1
р
AlхGa1-хAs (х=0,25-0,3)
(2-5) ∙1018
Barrier layer
0.06
р
AlхGa1-хAs (х=0,25-0,3)
(0.8-1) ∙1018
Active layer
–
GaAs
undoped
–
Al0,2Ga0,8As
Barrier layer
0.06
n
AlхGa1-хAs (х=0,25-0,3)
(0.5-1) ∙1017
Wide-gap window
6
n
AlхGa1-хAs
(1-2)∙1018
(х=0,3-0,35)
Stop layer
0.1
–
AlхGa1-хAs
–
(х=0,9-1)
Buffer layer
–
n
GaAs
–
Substrate
–
n+
GaAs
–
2. Where is the [...]
2020-05-18meta-author
PAM XIAMEN offers 6″CZ Prime Silicon Wafer-1
Item8, 25pcs
Silicon wafer:
i. Diameter: 150 mm ± 0.5 mm,
ii. Thickness: 675μm ±25μm
iii. Doping: P type
iv. Orientation: (111) ± 0.5°
v. TTV: ≤ 5 μm
vi. Bow and Warp: ≤ 20 μm
Growth: CZ
[...]
2020-03-30meta-author
A novel method for estimating threshold voltage shifts of n-channel SiC MOSFETs under negative gate bias stresses has been proposed. In the proposed method, n-type SiC MOS capacitors were utilized instead of n-channel SiC MOSFETs. The n-type SiC MOS capacitors were exposed to ultraviolet [...]
2019-10-21meta-author