PAM-XIAMEN offer SiC substrate with Ag, Ti or Ni or Au metal layers with small chips:
1. Specifications of SiC Chip Substrate
No 1. PAM200508-SIC-AU
10×10mm SiC substrate / Ti(0.1um)-Ni(0.1um)-Au(2um), n type.
Grade: dummy
Thickness: approx. 350um
Backside surface: with metal films of Ti-Ni-Au
Metal thickness: Ti(0.1um)-Ni(0.1um)-Au(2um),
No 2. SiC Wafer with thermal oxide and LPCVD nitride or Silicon Carbide Wafer with the sputtering Cr/Au Layer, such as SiC wafer with 1um SiO2 by PECVD
No 3. SiC Metallization Wafer:
SiC Wafer with Ti coating on backside, thickness:100nm
2. Chip on SiC Substrate with Ag, Ti, Ni or Au Ohmic Contact Layer
The preparation of SiC devices includes many processes, such as SiC substrate growth, ion doping, plasma etching and formation of ohmic contact. Among them, the formation of ohmic contact is one of the most important processes for preparing devices on SiC chips. The formation of ohmic contact actually refers to the formation of a special contact state between the metal and the semiconductor. In this contact state, the resistance of the contact surface is much smaller than the resistance of the semiconductor itself. Since the direct contact between the metal and the surface of the SiC chip wafer cannot form an ohmic contact, it is necessary to perform annealing treatment after the metal contacts the surface of the SiC wafer to form a metal silicide layer between the contact metal and the SiC substrate wafer. The metal silicide layer can effectively reduce the potential barrier between the contact metal and the SiC wafer, thereby achieving ohmic contact between the contact metal and the surface of the SiC wafer.
In terms of metals for SiC ohmic contact, there is a wide range of options available, including Cr, Ni, TiN, TiW, NiCr, W, TiW, Ti, TiAl, Mo, WMo, AuTa, TiAu, Ta, WTiNi, TiC and other metals or alloy. The following table shows representative ohmic contact preparation methods, basic parameters and specific contact resistance results in recent years:
| Metal | N-type Carrier Concentration(cm-3) | Annealing Temperature (℃) | Contact resistance (ohm-cm2) |
| Ni | 1-10 x 1018 | >950 | 2.8 x 10-3-2.8 x 10-6 |
| Ti | 1 x 1020 | Unannealed | 2 x 10-5 |
| W | 3 x 1018 – 1 x 1019 | 1200-1600 | 5 x 10-3-1 x 10-4 |
| Mo | >1 x 1019 | – | 1 x 10-4 |
| Ta | >1 x 1019 | – | 1 x 10-4 |
| Ti-Al | 4.5 x1020 | 1000 | 1 x 10-3 |
| TiN | 1 x 1018 | 600 | 4 x 10-2 |
| TiW | 1.1 x 1019 | 950 | 2-6 x 105 |
| TiC | 1.3 x 1019 | 950 | 4 x 10-5 |
| TaC | 2.3 x 1019 | 1000 | 2.1 x 10-5 |
| CoSi2 | 1.1 x 1019 | 500/800 | 1.8 x 10-6 |
| NiSi2 | 1 x 1019 | 950 | 1.2-2.7 x 10-5 |
| TiC | 4 x 1019 | 300 | 1.3 x 10-5 |
| TiC | 1.3 x 1019 | Room temperature co-steaming | 7.4 x 10-7 |
| P-type Carrier Concentration(cm-3) | |||
| Ni | 1 x 1015, Al+/C+ injection | 1050 | 1.5 x 10-4 |
| Ti/Al | 3-5 x 1019 | 900 | 1.42 x 10-5 |
| Al-Ti | 1 x 1019 | 900 | 6.4 x 10-4 |
| Si/Pt | 1 x 1019 | 1100 | 2 x 10-4 |
| TiC | 2 x 1019 | 500, Al+ injection | 1.9 x 10-5 |
| Al/Si/Ti | 3-5 x 1019 | 950 | 9.6 x 10-5 |
| TiN | 1 x 1019 | 650, FIB deposition | 4.4 x 10-5 |
| Pd | 5 x 1019 | 700 | 5.5 x 10-5 |
| Au/Ti/Al | 3-5 x 1019 | 950 | 1.6 x 10-5 |
| CrB2 | 1.3 x 1019 | 1100 | 8.2 x 10-5 |
It can be clearly seen from the table that there are various problems in the ohmic contact of silicon carbide chip materials at present:
- The composition and thickness of the metal layer forming the ohmic contact are uncertain;
- The time, temperature, atmosphere and other process parameters of the alloying annealing process for forming ohmic contacts are very different;
- The ohmic contact specific contact resistance results obtained are uneven, and the repeatability is poor;
The main reason for these problems is that the mechanism and physical model of ohmic contact formation are not clear enough.
At present, the specific contact resistance of ohmic contacts of n-type and p-type SiC MOSFET chip is usually in the range of 10-5-10-6 ohm*cm2 and 10-4-10-5 ohm*cm2, respectively, and the result of specific contact resistance is highly dependent on the carrier concentration on the wafer surface, the metal selection, the pretreatment of the wafer surface, and the conditions of the metallization thermal annealing. In order to obtain a good ohmic contact, the use of ion implantation to increase the carrier concentration on the SiC wafer surface, high-temperature alloying annealing, and the alloys or other compounds are widely used. The surface of SiC material is divided into Si plane and C plane. The difference of crystal plane has a great influence on the result of the electrical characteristics of SiC chip ohmic contacts. Generally, ohmic contacts are mostly made on the Si surface. At present, the ohmic contact of n-type SiC chip wafer from SiC chip manufacturers is mainly obtained by metallization annealing of Ni-based metal at 950-1050℃, and its specific contact resistance Pa on the SiC system on chip can basically meet the requirements of device applications. But for p-type SiC materials, the higher barrier height of the contact makes it more difficult to form a low specific contact resistance. Usually, A-Ti metal and silicide are metallized and annealed at 900-1180℃.
For more information, please contact us email at victorchan@powerwaywafer.com and powerwaymaterial@gmail.com