New graphene fabrication method uses silicon carbide template

New graphene fabrication method uses silicon carbide template

New graphene fabrication method uses silicon carbide templates to create desired growth

Graphene transistors. Georgia Tech researchers have fabricated an array of 10,000 top-gated graphene transistors, believed to be the largest graphene device density reported so far.

( — Researchers at the Georgia Institute of Technology have developed a new “templated growth” technique for fabricating nanometer-scale graphene devices. The method addresses what had been a significant obstacle to the use of this promising material in future generations of high-performance electronic devices.

The technique involves etching patterns into the silicon carbide surfaces on which epitaxial graphene is grown. The patterns serve as templates directing the growth of graphene structures, allowing the formation of nanoribbons of specific widths without the use of e-beams or other destructive cutting techniques. Graphene nanoribbons produced with these templates have smooth edges that avoid electron-scattering problems.

“Using this approach, we can make very narrow ribbons of interconnected graphene without the rough edges,” said Walt de Heer, a professor in the Georgia Tech School of Physics. “Anything that can be done to make small structures without having to cut them is going to be useful to the development of graphene electronics because if the edges are too rough, electrons passing through the ribbons scatter against the edges and reduce the desirable properties of graphene.”

The new technique has been used to fabricate an array of 10,000 top-gated graphene transistors on a 0.24 square centimeter chip – believed to be the largest density of graphene devices reported so far.

The research was reported Oct. 3 in the advance online edition of the journal Nature Nanotechnology. The work was supported by the National Science Foundation, the W.M. Keck Foundation and the Nanoelectronics Research Initiative Institute for Nanoelectronics Discovery and Exploration (INDEX).

In creating their graphene nanostructures, De Heer and his research team first use conventional microelectronics techniques to etch tiny “steps” – or contours – into a silicon carbide wafer. They then heat the contoured wafer to approximately 1,500 degrees Celsius, which initiates melting that polishes any rough edges left by the etching process.

They then use established techniques for growing graphene from silicon carbide by driving off the silicon atoms from the surface. Instead of producing a consistent layer of graphene one atom thick across the surface of the wafer, however, the researchers limit the heating time so that graphene grows only on the edges of the contours.

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