The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device [...]
2020-01-13meta-author
Helium implantation-induced layer splitting of InP in combination with direct wafer bonding was utilized to achieve low temperature layer transfer of InP onto Si(1 0 0) substrates. InP(1 0 0) wafers with 4 inch diameter were implanted by 100 keV helium ions with a dose of 5 × 1016 cm−2. Then [...]
2019-12-09meta-author
PAM XIAMEN offers FZ & MCZ silicon ingot and silicon wafer:
Description
Growth Method
—
MCZ
Single crystal size
inch
2 – 8
Conductivity Type
—
N
P
Doped elements
—
P/Sb
B
Crystal Orientation
—
<111>
<110>
<100>
<111>
<110>
<100>
Resistivity
Ω.cm
0.0015-100
0.001-100
RRG
%
20
20
Oxygen Concentration
atoms/cm3
1.00E+18
1.00E+18
Carbon Concentration
atoms/cm3
5.00E+16
5.00E+16
Diameter
mm
55-157
55-157
Length
mm
50-500
50-500
Dislocation
EA/cm2
N/A
N/A
Swirl(After Oxidation)
—
N/A
N/A
Remarks:The above parameters can be customized.
FAQ about MCZ Silicon Wafers
Q:This is just a curiosity, but let me ask about the production method of [...]
2019-02-27meta-author
PAM XIAMEN offers (110) Silicon Substrates.
If you don’t see what you need then please email at sales@powerwaywafer.com.
Diam
(mm)
Material
Dopant
Orient.
Thck
(μm)
Surf.
Resistivity
Ωcm
Comment
6″
p–type Si:B
[110] ±0.5°
390 ±10
C/C
>10
Prime, 2Flats, Empak cst
6″
p–type Si:B
[110] ±0.5°
500
P/E
FZ >10,000
Prime, 2Flats, Empak cst, TTV<5μm
6″
p–type Si:B
[110] ±0.5°
200
P/P
FZ 1–2
Prime, 2Flats, Empak cst
6″
p–type Si:B
[110] ±0.5°
200
P/P
FZ 1–2
SEMI Prime, 2Flats, Empak cst
6″
p–type Si:B
[110] [...]
2019-02-22meta-author
PAM-XIAMEN can offer epitaxy wafer of silicon for manufacturing integrated optical waveguide devices. The silicon epi wafer we offer is grown core layer of Si and lower cladding layer of SiO2 on Si substrate and the waveguide structure is ridged. Due to the large [...]
2022-09-05meta-author
PAM XIAMEN offers 4″ Silicon Wafer.
Material
Orient.
Diam.
Thck
(μm)
Surf.
Resistivity
Ωcm
Comment
n-type Si:Sb
[211] ±0.5°
4″
1,500 ±15
P/P
0.01-0.02
SEMI Prime, TTV<1μm
n-type Si:Sb
[211] ±0.5°
4″
1600
C/C
0.01-0.02
SEMI Test, Wafers can be polished for additional fee
n-type Si:P
[111]
4″
1200
P/P
35-85
SEMI Prime
n-type Si:P
[111] ±0.5°
4″
1500
P/E
>20 {24-29}
SEMI Prime, TTV<5μm, in Empak cassettes of 2 wafers
n-type Si:P
[111] ±0.5°
4″
250
P/E
18-25
SEMI Prime
n-type Si:P
[111] ±0.5°
4″
500
P/P
11-15
SEMI Prime, Both-sides Epi Ready polished
n-type Si:P
[111]
4″
280
P/E
1.3-2.7
SEMI Prime
n-type Si:P
[111] ±0.5°
4″
280
P/E
1.3-2.7
SEMI Prime
n-type [...]
2019-03-05meta-author