Xiamen Powerway Advanced Material Co.,Ltd., a leading supplier of LT-GaAs wafer, offers low-temperature grown gallium arsenide on GaAs substrate wafer. Our LT-GaAs epi layer has excellent properties, GaAs films with LT-GaAs layers were grown by molecular beam epitaxy (MBE) method at a low temperature substrate. The grown structures were different with the thickness of LT GaAs layers and its arrangement in the film. Investigations of crystalline properties of the grown structures were carried out by the methods of X-ray diffraction (XRD) and transmission electron microscopy (TEM). The availability improve boule growth and wafering processes. Our customers can benefit from the increased device yield expected when developing advanced transistors on a square substrate.
1. LT-GaAs Epiwafer Specifications
1.1 2″ LT-GaAs Wafer Parameters
Diameter(mm)Ф 50.8mm ± 1mm
Marco Defect Density≤5 cm-2
Resistivity(300K) >10^8 Ohm-cm
Carrier lifetime<15ps or <1ps
Useable Surface Area≥80%
Polishing: Single side polished
Substrate: GaAs substrate
1.2 Low-Temperature Grown GaAs Epitaxial Structure
2″ LT-GaAs Epitaxial Wafer (PAM160628-LTG)
|1||GaAs buffer epi-layer||–|
|SI-GaAs Substrate, 350um Thick|
2. About Low-Temperature Growth of GaAs
Low-temperature epitaxial growth of GaAs is known from the literature has a lattice constant larger than the lattice constant of high temperature GaAs. This is due to the adsorption of excess As at low temperatures. There are stresses at the interface of LT GaAs / GaAs due to the difference in lattice parameters. To reduce the accumulated stress the presence of misfit dislocations lying in the interface is required. The most profitable way to the formation of such misfit dislocations is bending the existing threading dislocations, the so-called process without activation. On the TEM images can be seen that in the annealed samples with a 700 nm LT-GaAs layer the dislocations are partly bent along the interface of LT-GaAs/GaAs and in the samples without annealing the dislocations are changing its direction of propagation at the interface. However in the samples with 170 nm and 200 nm LT-GaAs layers such the features are observed much less often. Therefore, with increasing the LT-GaAs layer thickness the stresses at the interface of LTGaAs/GaAs are increasing and the dislocations are bent more effectively. In addition worth noting that position of LT-GaAs layer in the GaAs/Si(001) film did not play a significant role in changing the density of threading dislocations.
The crystalline perfection of the GaAs films with low-temperature-grown GaAs (LTG-GaAs) layers and the GaAs films without ones was comparable. In the GaAs/Si structures with LT-GaAs layers the crystal lattice rotation round the direction was detected. It was found that in the LT-GaAs/Si layers the arsenic clusters are formed, as it occurs in the LT-GaAs/GaAs system without dislocation. It is shown that large clusters are formed mainly on the dislocations. It means the dislocations are a kind “channels” for atoms of As. Using δ-In we managed to obtain an ordered array of As clusters. The clusters array proved to have no effect on the density and the propagation path of threading dislocations. Thus, the dislocations affect the position and size of As clusters, and the clusters do not affect the evolution of the threading dislocations system. With increasing LT-GaAs buffer layer thickness the stresses at the interface of LTGaAs/GaAs are increasing and the dislocations are more bent.
3. Particle Pollution Cleaning Method for LT-GaAs Wafer
The simple cleaning method for low temperature grown GaAs is as follows:
Step 1: wash with a certain material for xx minutes. The goal is to remove oil and impurities.
Step 2: wash with a certain material for xx minutes, the goal is to remove acetone
Step 3: wash with a certain material for xx minutes. The goal is to remove ethanol.
It can be cleaned up in three steps. During the cleaning process, soak in a beaker and shake the beaker.
For more information please contact us at firstname.lastname@example.org.
4. Q&A of Low-Temperature Grown GaAs based Epitaxial Wafer
Q 1: What’s the structure please? Is LT-GaAs layer grown on the GaAs substrate?
A: Yes, structure is GaAs/LT-GaAs.
Q 2: What is the band that the LT-GaAs corresponds to?
Q 3: What’s the carrier lifetime?
A: Lifetime <15ps or <1ps
Q 4: We bought LT GaAs on GaAs wafer from you more than 1 year ago. We like the quality of your LT GaAs, but for our experiments, we need to transfer LT GaAs to other substrate (quartz etc.).Can you grow AlAs then LT GaAs on semi-insulating GaAs wafer so that we can layer transfer LT GaAs?
A: Please just give me the structure and layer thickness, so that we can check.
Q 5: I think what we want is(from bottom up) GaAs substrate/AlAs(300nm)/LT GaAs (1-2um).
A: Yes we can grow this structure with AlAs300nm.
Q6: I have one more question, what quality control checks do you perform either post growth or during growth? In particular, we are most concerned on the thickness, resistivity and carrier lifetime of the LT-GaAs layer.
A: Quality control of the low-temperature GaAs based mainly on experience in regulating growth conditions, of course the test is the most important measure of the quality of the material. LT GaAs thickness should be 120nm+/-5%, the resistivity is no specific data, and life time< 1ps.