4 inch Test Grade Silicon Wafer with Single Side Polished

4 inch Test Grade Silicon Wafer with Single Side Polished

PAM-XIAMEN can offer 4 inch test grade silicon wafer with single side polished. The parameters for 4″-SSP Si wafer at test grade are as follows:

Test grade Silicon Wafer

1. Parameters of Si Single Crystal Wafer at Test Grade

PAM-210310-Si wafer

Sl NoItemSpecifications
1Growing MethodCZ
2Wafer Diameter100±0.5 mm
3Wafer Thickness525±25 μm
4Wafer Surface Orientation<100>±0.5º
5TypeP type
6DopantBoron
7Dislocation DensityLess than 5000/cm2
8Resistivity2-8 Ohm-cm
9Radial Resistivity Variation(max.)N/A
10Flatness
10aBOW(max.)50 μm
10bTIRN/A
10cTTV10 μm
10dWARPN/A
11Primary Flat
11aLength32.5±2.5 mm
11bOrientation(110)±0.2º as per SEMI Standard
11cSecondary FlatAs per SEMI Standard
12Front Surface FinishMirror Polished
13Max. particles of size ≥0.3μm< 30pcs
14Scratches, Haze, Edge Chips, Orange Peel&Other defectsN/A
15Back SurfaceEtched
16Packing Requirementwafer cassette

2. Future Development of Test Grade Silicon Wafer

High-purity single crystal silicon is an important semiconductor material. A p-type silicon semiconductor can be formed by adding a small amount of group IIIA elements to the monocrystalline silicon; a small amount of group VA elements are added to form an n-type semiconductor. The p-type semiconductor and the n-type semiconductor are combined to form a p-n junction. In addition, the diodes, triodes, thyristors, field effect transistors and various integrated circuits (including chips and CPUs in computers) are all made of silicon. Silicon wafer test grade is a promising material in the development of energy.

Currently, the photovoltaic industry is still dominated by P-type silicon wafers. P-type silicon wafers are doped with boron. The segregation coefficient of boron and silicon is equivalent, and the dispersion uniformity is easy to control. Therefore, the manufacturing process is simple, and the cost is lower, but the highest efficiency has a limitation. N-type silicon wafers are doped with phosphorus, and the compatibility of phosphorus with silicon is poor. The distribution of phosphorus is uneven when the rod is drawn, and the process is more complicated. However, the N-type test grade silicon wafer usually has a longer lifespan, and the battery efficiency can be higher. The improvement of efficiency refers to the improvement of photoelectric conversion efficiency. So in the future, the technological development of silicon wafers is mainly based on improving efficiency and reducing costs.

powerwaywafer

For more information, please contact us email at [email protected] and [email protected].

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