Vertical GaN Homoepitaxial Wafers for Power Devices

Wide-bandgap semiconductors, exemplified by gallium nitride (GaN), have become the core material for next-generation power electronic systems due to their high breakdown electric field, high electron saturation velocity, and favorable thermal conductivity. In the realm of power devices, vertical architectures offer distinct advantages over conventional lateral devices (such as high-electron-mobility transistors): current flows along the epitaxial growth direction, enabling a linear increase in breakdown voltage by simply thickening the drift layer without enlarging chip area. Additionally, the internal peak electric field is kept away from the device surface, suppressing current collapse and potentially enabling avalanche capability, thereby greatly enhancing reliability.

Among various vertical GaN power devices (e.g., trench metal-oxide-semiconductor field-effect transistors, or trench MOSFETs), the epitaxial foundation is an n-p-n homojunction stack. The material quality, interface characteristics, and process compatibility of this stack directly determine final device performance and yield. Therefore, a deep understanding of the surface and interface physical phenomena and process-induced defect mechanisms involved in the fabrication and processing of GaN n-p-n structures is critical for advancing vertical power devices.

1. Advantages of Vertical GaN Homoepitaxy and Fundamental Material Supply

Unlike heteroepitaxy on silicon, sapphire, or silicon carbide, GaN homoepitaxy completely eliminates lattice and thermal mismatches, reducing dislocation density from 10⁸–10¹⁰ cm⁻² (in heteroepitaxy) down to 10⁴–10⁶ cm⁻². Low defect density means fewer leakage paths, lower carrier trap concentrations, and higher breakdown voltage – a prerequisite for fabricating high-performance vertical power devices.

To meet the core material requirements for vertical power devices (such as MOSFETs, CAVETs, etc.), PAM-XIAMEN provides high-quality GaN homoepitaxial wafers with the following typical structures:

Epitaxial Layer	Material	Thickness	Doping
Top layer	n-GaN	–	–
Drift layer	p-GaN	0.8–1 µm	Mg: *
Channel layer	n-GaN	–	–
Substrate	n-GaN	–	–

 

2. Surface States and Fermi-Level Pinning in Vertical GaN n-p-n Structures

When an n-p-n structure is cleaved or etched to form mesas and trenches, the exposed nonpolar (m-plane, i.e., (10-10)) surface of GaN develops complex surface states, leading to Fermi-level pinning. This phenomenon directly affects sidewall leakage behavior and gate interface stability. Freter et al. (2020) systematically investigated clean-cleaved and air-exposed GaN n-p-n structures using scanning tunneling microscopy/spectroscopy (STM/STS), revealing the physical origins of surface pinning on different doped regions.

2.1 Pinning Mechanism on Clean Cleaved Surfaces

On n-type GaN(10-10) surfaces, the Fermi level is primarily pinned by intrinsic surface states – specifically, gallium (Ga)-derived dangling bonds. The minimum of the dispersion relation for these surface states lies approximately 1 eV below the conduction band minimum, resulting in upward surface band bending. In tunneling spectra, this manifests as an apparent bandgap smaller than the true bandgap and a positive shift of the conduction-band current onset voltage.

On p-type GaN(10-10) surfaces, the situation is entirely different. Intrinsic nitrogen (N) dangling bond states lie close to the valence band maximum and cannot effectively pin the Fermi level. Experiments show a very small apparent bandgap and tunneling current originating from midgap defect states, indicating that pinning arises from extrinsic defect states. STM images reveal a high density of cleavage steps and kinks on the p-type layer surface. These step edges (especially facets along the c‑axis direction) introduce half-filled localized states in the midgap, becoming the dominant Fermi-level pinning centers for the p‑type GaN surface. In contrast, on n‑type layers, the intrinsic surface state density is much higher than the step state density, so step effects are not significant.

Fig. 1 Typical current–voltage (I‑V) tunneling spectra (logarithmic scale) on clean cleaved n‑type and p‑type GaN(10-10) surfaces, together with a topographic image of the p‑type surface

2.2 Passivation Effect Induced by Air Exposure

After exposing the cleaved surface to air (especially water molecules), then reintroducing it into ultrahigh vacuum with mild annealing, clear changes appear in the tunneling spectra: the density of pinning states on the p‑type surface decreases, and the pinning level shifts toward the valence band maximum; on the n‑type surface, the conduction-band current onset voltage drops from about +1V to +0.5V, indicating reduced band bending. Freter et al. attribute this to dissociative adsorption of water molecules: OH groups bind to Ga atoms, and H atoms bind to N atoms. Hydroxylation pushes the Ga and N dangling bond states toward the valence band maximum, partially passivating both intrinsic and step defect states. However, this passivation is incomplete – the p‑type surface retains some step-related leakage channels, and the n‑type surface does not achieve a complete flat-band condition. Therefore, relying on natural passivation by air exposure is uncontrollable in device processing, and engineered dielectric deposition and passivation schemes are necessary.

Fig. 2 Schematic band diagrams for clean GaN(10-10) surface and hydroxylated GaN(10-10) surface

3. Challenges in Device Processing: p-GaN Activation and “Killer Defects”

Fabricating high-quality n-p-n homoepitaxial wafers into vertical transistors faces a core processing challenge – acceptor activation of the p‑type GaN layer. During MOCVD epitaxy of the n⁺ source layer, a hydrogen ambient causes Mg acceptors to form electrically neutral Mg‑H complexes (so-called “hydrogen passivation”). Because the p‑layer is capped by the overlying n⁺ layer, hydrogen atoms cannot escape vertically. Consequently, high-temperature annealing (typically 750°C in nitrogen ambient) is required to drive hydrogen out laterally through the mesa sidewalls, thereby reactivating the Mg acceptors.

Kamiński et al. (2025) fabricated npn test structures on a vertical trench MOSFET process platform and, using electrical characterization, atomic force microscopy (AFM), scanning electron microscopy (SEM), and TCAD simulations, systematically analyzed two major negative impacts of this process:

3.1 Insufficient Activation and Low Effective Doping Concentration

Experiments show that the Mg chemical doping concentration is 3.3×10¹⁸cm⁻³, but the activated effective acceptor concentration (N_A-N_D) is only about 1.5×10¹⁷cm⁻³ – an activation yield below 5%. Low hole concentration degrades threshold voltage controllability and increases on‑resistance.

Fig. 3 Capacitance–voltage (C‑V) characteristics of a circular npn test structure after Mg activation anneal, and the extracted effective acceptor concentration profile

3.2 High-Temperature Induced “Killer Defects” in Vertical GaN Structure

More severely, the activation annealing process randomly introduces local defects inside the device. By statistically analyzing breakdown voltage and leakage current of circular npn diodes with different diameters, Kamiński et al. found that after annealing, the breakdown voltage yield of large‑area devices drops sharply. Fitting defect density with a Poisson distribution model confirms a significant increase in the areal density of “killer defects” after annealing. Under reverse bias, these defects form low‑barrier leakage paths, causing off‑state current to surge (even to the milliampere level) and leading to premature device failure. These defects are likely defect clusters formed by migration and aggregation of point defects at high temperatures; their local electric field lowers the barrier, inducing punch‑through leakage. Notably, using low‑dislocation‑density ammonothermal GaN substrates significantly suppresses the formation of such defects, further highlighting the importance of high‑quality homoepitaxy.

Fig. 4 Poisson distribution model fitting of the areal density of “killer defects” in vertical GaN npn structures before and after annealing

Whether you need GaN epiwafer for research or for industrial applications, please contact us email at [email protected] and [email protected].

 

References:

1. Freter, L., Wang, Y., Schnedler, M., Carlin, J. F., Butté, R., Grandjean, N., … & Ebert, P. (2020). Interplay of intrinsic and extrinsic states in pinning and passivation of m-plane facets of GaN npn junctions. Journal of applied physics, 128(18).
2. Kamiński, M., Abendroth, K., Gołębiowska, A., Szczepański, A., Urbanowski, K., Brzozowski, E., … & Taube, A. (2025). On the origin of off-state leakage current in npn vertical structures for GaN-based trench-MOSFETs. Power Electronic Devices and Components, 11, 100086.