2-4.Wafer Surface Orientation
Denotes the orientation of the surface of a wafer with respect to a crystallographic plane within the lattice structure.
In wafers cut intentionally “off orientation”, the direction of cut is parallel to the primary at, away from the secondary at.
Measured with [...]
2018-06-28meta-author
5-5-4 Patterned Etching of SiC for Device Fabrication
At room temperature, there are no known conventional wet chemicals that etch single-crystal SiC. Most
patterned etching of SiC for electronic devices and circuits is accomplished using dry etching techniques.
The reader should consult References 122–124 which contain summaries [...]
2018-06-28meta-author
5-4-3 Growth of Hexagonal Polytype SiC Wafers
In the late 1970s, Tairov and Tzvetkov established the basic principles of a modified seeded sublimation growth process for growth of 6H-SiC. This process, also referred to as the modified Lely process,was a breakthrough for SiC in that [...]
2018-06-28meta-author
3-1. Large Point Defects
Defects which exhibit a clear shape to the unassisted eye and are > 50 microns across. These features include spikes, adherent particles, chips and craters. Large point defects less than 3 mm apart count as one defect.
2018-06-28meta-author
2-14.Masking Defects
also referred to as “Mound”
When one defect prevents the detection of another defect, the undetected defect is called the masked defect.
A distinct raised area above the wafer frontside surface as viewed with diffuse illumination.
2018-06-28meta-author
5-5-3 SiC Contacts and Interconnect
All useful semiconductor electronics require conductive signal paths in and out of each device as well as
conductive interconnects to carry signals between devices on the same chip and to external circuit
elements that reside off-chip. While SiC itself is theoretically capable [...]
2018-06-28meta-author