Due to the high growth pressure and relatively low temperature, Al is not easily evaporated and lost in the liquid-phase method. Adding Al to the flux used in the liquid-phase method can easily obtain P-type silicon carbide (SiC) crystals with high carrier concentration, solving the problem of missing P-type silicon carbide substrate in the SiC industry. PAM-XIAMEN is able to supply liquid-phase grown p-type silicon carbide substrates, with properties such as low resistance, high doping concentration, and high quality. The p-type substrates can meet the preparation requirements of bipolar devices such as n-channel IGBT and GTO. Please refer to the following tables for specific specifications:
1. P-Type Silicon Carbide Substrate Specifications
1.1 50.8mm P-Type 4H/6H SiC Wafer
Item | 2 inch P-Type SiC Substrate | |||
Grade | Ultra Prime Grade | Industrial Grade | Test Grade | |
Diameter | 50.8±0.38mm | |||
Thickness | 350±25um | |||
Polytype | 4H or 6H | |||
Orientation | off axis 2~4° toward [11-20]±0.5° | |||
Primary Flat Orientation | {10–10}±5.0° | |||
Primary Flat Length | 15.9±1.7mm | |||
Secondary Flat Orientation | Si face up: 90° CW.from prime flat ±5.0° | |||
Secondary Flat Length | 8.0±1.7mm | |||
MPD* | <0.1cm-2 | |||
Resistivity * | ≤0.1Ω·cm | ≤0.3Ω·cm | ||
LTV | ≤2.5μm | |||
TTV | ≤5μm | |||
Bow | ≤15μm | |||
Warp | ≤25μm | ≤30μm | ||
Roughness* | Polishing | Ra≤1nm | ||
CMP | Ra≤0.2nm | Ra≤0.5nm | ||
Edge Cracks by High Intensity Light | None | 1 allowed, ≤1mm | ||
Hex Plates by High Intensity Light* | Cumulative area≤0.05% | Cumulative area≤3% | ||
Polytype Areas by High Intensity Light* | None | Cumulative area≤5% | ||
Visual Carbon Inclusions | Cumulative area≤0.05% | Cumulative area≤3% | ||
Scratches on Si Face by High Intensity Light | None | 8 scratches to 1×wafer diameter cumulative length | ||
Edge Chips by High Intensity Light | None permitted≥0.2mm width and depth | 5 allowed, ≤1mm each | ||
Si-Face Contamination by High Intensity Light | None | |||
Edge Exclusion | 1mm | 5mm | ||
Package | Single Wafer Box or Multi Wafer Box |
“*” value is applicable to the entire wafer surface except for edge exclusion areas
1.2 100mm P-Type 4H-SiC Wafer
Item | 4 inch P-Type 4H-SiC Substrate | |||
Grade | Ultra Prime Grade | Industrial Grade | Test Grade | |
Diameter | 99.5~100mm | |||
Thickness | 350±25um | |||
Polytype | 4H | |||
Orientation | off axis 2~4° toward [11–20]±0.5° | |||
Primary Flat Orientation | {10–10}±5.0° | |||
Primary Flat Length | 32.5±2.0mm | |||
Secondary Flat Orientation | Si face up: 90° CW.from prime flat ±5.0° | |||
Secondary Flat Length | 18.0±2.0mm | |||
MPD* | <0.1cm-2 | |||
Resistivity * | ≤0.1Ω·cm | ≤0.3Ω·cm | ||
LTV | ≤2.5μm | ≤10μm | ||
TTV | ≤5μm | ≤15μm | ||
Bow | ≤15μm | ≤25μm | ||
Warp | ≤30μm | ≤40μm | ||
Roughness* | Polishing | Ra≤1nm | ||
CMP | Ra≤0.2nm | Ra≤0.5nm | ||
Edge Cracks by High Intensity Light | None | Cumulative length≤10mm,single length≤2mm | ||
Hex Plates by High Intensity Light* | Cumulative area≤0.05% | Cumulative area≤0.1% | ||
Polytype Areas by High Intensity Light* | None | Cumulative area≤3% | ||
Visual Carbon Inclusions | Cumulative area≤0.05% | Cumulative area≤3% | ||
Scratches on Si Face by High Intensity Light | None | Cumulative≤1×wafer diameter | ||
Edge Chips by High Intensity Light | None permitted≥0.2mm width and depth | 5 allowed, ≤1mm each | ||
Si-Face Contamination by High Intensity Light | None | |||
Edge Exclusion | 3mm | 6mm | ||
Package | Single Wafer Box or Multi Wafer Box |
“*” value is applicable to the entire wafer surface except for edge exclusion areas
We just simplified introduce P-type silicon carbide substrate applications in IGBT ( Insulate-Gate Bipolar Transistor).
2. IGBT on P-Type SiC Substrate
IGBT= MOSFET+BJT, it is a non-on or off switch. MOSFET=IGFET (Metal Oxide Semiconductor Field Effect Transistor, or Insulated Gate Field Effect Transistor). BJT (Bipolar Junction Transistor, bipolar junction transistor, also known as triode), bipolar means that there are both electrons and holes participating in the conduction process during operation. Generally, there is a PN junction participating in conduction.
A simple example is given: look at the upper part, the gate+emitter+N is completely a vertical MOSFET structure, but a P-type semiconductor is added at the bottom to form a PNP-type BJT.
The principle of energization is divided into two parts:
1)Voltage is applied to the gate, and the upper part is turned on, then the entire device is transformed into an NP structure from the top to the bottom.
2)Voltage is applied to the collector, so the lower half is turned on, and the PN junction is turned on normally.
Finally, the current flows from the collector to the emitter. Because of the existence of the PN junction, there are electrons and holes that conduct electricity.
Give a few examples.
Connecting wires to the above structure, it can be used as an IGBT single tube. The appearance is similar to the MSOFET; after all, it is also used as a switch.
If several IGBTs are put together, or put together with other devices, they can be used as IGBT modules.
IGBT merges the advantages of BJT and MOSFET, such as low driving power and reduced saturation voltage.
3. Development of SiC IGBT
The development of silicon carbide IGBT is shown below:
1996: first 6H-SiC Trench gate IGBT
1999: first 4H-SiC Trench gate pIGBT
2005: first 4H-SiC Planar gate nIGBT
2007: charge storage layer introduced to JFET region
2010: free-standing technology proposed
2012: first 12kV/10A SiC IGBT module
2015: * 15kV/40A IGBT module
* first 7kV/8kW SST
* first 32kV Marx Generator
* 27kV SiC nIGBT
Structurally, the IGBT mainly has three development directions:
1) Longitudinal structure: non-transparent collector area NPT type, buffer layer PT type, transparent collector area NPT type, FS electric field cut-off type;
2) Gate structure: planar gate structure, Trench-trench structure;
3) Substrate: epitaxial growth technology and type.
In order to inherit the structure of the MOSFET with an N-type substrate, it is necessary to grow an IGBT on a P-type silicon carbide substrate. The P-type silicon carbide substrate generally refers to an Al-doped silicon carbide substrate. Al is +3 valence, replacing part of the +4 valence Si in SiC, forming Al and a +1 valence hole. Holes are P-type semiconductors. In addition to Al, other trivalent elements will also be used as P-type dopants, including B, Ga, In and so on. Doping silicon carbide with nitrogen and phosphorus can form n-type semiconductors, while doping with aluminum, boron, gallium, and beryllium will form p-type semiconductors. Aluminum-doped silicon carbide is a type II semiconductor, but boron-doped silicon carbide is a type I semiconductor. The heterojunction types are as follows: Type I heterojunction: a small forbidden band is enclosed in a large forbidden band; Type Ⅰ’heterojunction: two forbidden bands intersect; Type Ⅱ heterojunction: Two forbidden bands are staggered.
For more information, please contact us email at victorchan@powerwaywafer.com and powerwaymaterial@gmail.com.