As one of leading SiC epi wafer suppliers, PAM-XIAMEN offers SiC epi wafer, and the SiC epi wafers type includes N type and P type. The SiC epi wafer thickness from 1um to 250um can be produced, and the silicon carbide epi wafer prices are competitive. What is SiC epi wafer? SiC epitaxial wafer is an intermediate link in the core of the SiC industry chain. At present, a whole set of industrial systems from silicon carbide substrates and SiC epi wafers to device preparation have been formed in the world. In the epi wafer market, high-quality SiC epitaxy are the basic materials of SiC power devices. The current development trend of silicon carbide epitaxial materials required by power electronic devices at home and abroad is developing in large diameter, low defects, high uniformity and etc.
1. Specifications of 4-inch SiC Epi Wafer
Item 1:
PAM201221-SIC-EPI
| SiC Substrate | |
| Diameter | 100mm |
| Thickness | 350um |
| Polytype | 4H-SiC |
| Conductivity | N-type |
| Off-orientation toward | 4-degree off-axis |
| MPD | ≤1/cm2 |
| Resistivity | 0.015~0.028 ohm-cm |
| Surface finish | Double side polished |
| Epi layer | |
| Buffer: | |
| Thickness | 0.5um, n-type |
| Doping level | 1E18cm3 |
| Epi 1: | |
| Thickness | 6um+/-5% |
| n-Doping level | 5.2E15/cm3 |
Item 2:
PAM210514-SIC-EPI
| SiC Substrate | |
| Diameter | 100mm |
| Thickness | 350um |
| Polytype | 4H-SiC |
| Conductivity | N-type |
| Off-orientation toward | 4-degree off-axis |
| MPD | ≤1/cm2 |
| Resistivity | 0.015~0.028 ohm-cm |
| Surface finish | Double side polished |
| Epi layer: | |
| Buffer: | |
| Thickness | 0.5um, n-type |
| Doping level | 1E18cm3 |
| Epi 1: | |
| Thickness | 6um+/-5% |
| n-Doping level | <1E15/cm3 |
| Low O, B, P and Al elements: | B<0.06PPM;P<0.05PPM;Al<0.01PPM; without O |
2. SiC Epi in the Fields of Low Voltage, Medium Voltage and High voltage
In terms of application, we generally divide silicon carbide into three areas, namely low voltage, medium voltage and high voltage. In the case of low voltage, it is mainly for some consumer electronics, such as PFC and power supply; medium voltage is mainly for automotive electronics, and medium voltage is also the main application direction for the development of SiC epi wafer in the future. The third is the application end with relatively high voltage levels, such as rail transit and power grid systems above 3300V.
At the same time, we can see that silicon carbide and gallium nitride are still in a competitive relationship in the medium and low-voltage field, but in the high-voltage field, from the perspective of material maturity, silicon carbide has a unique advantage. However, it is a pity that up to now, there has not been a mature product in the high-voltage field. The SiC epi wafer for the high-voltage field is in the stage of research and development all over the world, but in the middle and low voltage silicon carbide epitaxial wafers are already applied in diodes and MOSFET products in the market.
3. 100mm 4H SiC Epitaxial Wafer Norm
This norm applies to 4H silicon carbide (4H-SiC) epitaxial wafers. The SiC wafer production is mainly used to manufacture power semiconductor devices or power electronic devices.
3.1 Requirements of 4H-SiC Epitaxial Growth in 4 Inch
The substrate is a (0001) silicon surface 4H-SiC wafer with an angle of 4° in the <11-20> direction. The ratio of 4H crystal type to the total area of the silicon carbide wafer should not be less than 90%. The surface of the wafer can be polished on one side or on both sides. The silicon surface of the wafer should be chemically mechanically polished with a surface roughness of less than 0.5 nm. The number of cleanable particles on the surface of the wafer (diameter ≥0.5 um) does not exceed 15/piece.
3.2 Epitaxial Quality Requirements for the SiC wafer
Surface defects of SiC epitaxy should meet the requirements of the following table.
| Item | Maximum Allowable Limit | |
| Industrial Grade | Research Grade | |
| Carrots | ≤80pcs/wafer | ≤100pcs/wafer |
| Comets | ||
| Triangles | ||
| Downfalls | ||
| Edge Removal | 3 mm | 3 mm |
The surface roughness of SiC wafer in size of 4” should be less than 5.0 nm in the entire 4H-SiC epitaxial wafer range.
The thickness uniformity of the 4-inch SiC epitaxial layer should meet: industrial grade ≤5% and research grade ≤7%
Doping concentration uniformity for industrial grade should be ≤30%, and that for research grade should be ≤35%.
4. FAQ about SiC Epitaxy
Q1: I looked at the SiC homoepitaxial wafers on your company website before, and they all have buffer layer. I would like to ask what is the function of the intermediate buffer layer? What effect will it have on the epitaxial layer if directly epitaxial without a buffer layer?
A: The role of the intermediate buffer layer in SiC homoepitaxy is to reduce defect density and provide epitaxial yield.
Q2: Is there a big difference between the growth temperature of the buffer layer and the epitaxial layer of 4H-SiC epitaxial wafer?
A: There is little difference in growth temperature for buffer and epitaxial layer of 4H-SiC epi wafer.
For more information about SiC epi wafer, please refer to:
150mm 4H n-type SiC EPI wafers
Why do We Need Silicon Carbide Epitaxial Wafer?
For more information, please contact us email at victorchan@powerwaywafer.com and powerwaymaterial@gmail.com.