The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device [...]
2020-01-13meta-author
PAM XIAMEN offers 2″ Silicon Oxide Wafer
2″ Silicon Oxide Wafer
Diameter (mm): 50mm
Grade: Prime
Growth: CZ
Type/Dopant: any
Orientation: 100
Resistivity (Ohm-cm): any
Thickness (µm): 500±25μm
Tolerance (µm): any
Surface Finish: SSP
Flats: SEMI-Std.
TTV < (µm): any
Bow < (µm): any
Warp < [...]
2020-04-24meta-author
PAM-XIAMEN offers A Plane N-GaN Freestanding GaN Substrate
Item
PAM-FS-GAN A-N
Dimension
5 x 10 mm2 or 5 x 20 mm2
Thickness
380+/-50um
Orientation
A plane (11-20) off angle toward M-axis 0 ±0.5°
A plane (11-20) off angle toward C-axis -1 ±0.2°
Conduction Type
N-type / Si Doped
Resistivity (300K)
< 0.05 Ω·cm
TTV
≤ 10 µm
BOW
-10 µm ≤ BOW ≤ 10 µm
Surface Roughness:
Front side: Ra<0.2nm, epi-ready;
Back side: Fine Ground or polished.
Dislocation Density
≤ 5 x 106 cm-2
Macro Defect Density
0 cm-2
Useable Area
> 90% (edge exclusion)
Package
each in single wafer container, under nitrogen atmosphere, packed in class 100 clean room
For more information, please contact us email at victorchan@powerwaywafer.com and powerwaymaterial@gmail.com
2020-08-17meta-author
PAM XIAMEN offers 3″ Silicon Wafer-17 as follows, while silicon wafer list includes, but not limited to the following.
Silicon wafers, per SEMI Prime,
P/P 4″Ø×300±25µm,
p-type Si:B[100]±0.5°, Ro=(5-10)Ohmcm,
TTV<10µm, Bow<40µm, Warp<40µm,
Both-sides-polished, SEMI Flats (two),
Primary Flat length 32.5±2.5mm, orientation 110±1°。
Secondary Flat length 18±2mm, orientation 90°±5°
Sealed in Empak cassette
For [...]
2019-11-26meta-author
GaAs / AlGaAs / GaAs epi wafer in the diameter of 2” or 4” is available. This GaAs epitaxial wafer is applicable for semiconductor microwave devices and microwave monolithic integrated circuits. Here comes the typical structure of gallium arsenide epi wafer, please see below:
1. GaAs Wafer Epitaxial Structures
Structure 1:
2”GaAs/AlGaAs/GaAs epi wafer
S.No
Parameters
Specifications
1
GaAs substrate layer [...]
When SiC wafer is used as the substrate of RF devices, it is required that SiC should be semi insulating and its resistivity should be greater than 10 ^ 6 Ω· cm. In fact, the resistivity of silicon carbide should be very high, but [...]
2020-08-25meta-author