What are Annealed Silicon Wafer?

What are Annealed Silicon Wafer?

Annealed silicon wafer can be provided with low defect density from PAM-XIAMEN. The purpose of using annealed wafer is to eliminate defects on the silicon wafer surface and the component manufacturing area of the surface layer, and has a strong ability to capture heavy metal pollution, improving the chip yield.

silicon annealed wafer

1. Parameters of Silicon Annealed Wafer

PAM-210618-SI

Sl. No. Specification Value
1 Grade Prime
2 Growth Method CZ
3 Diameter 150 ± 0.3 mm
4 Type / Dopant N (Arsenic/ Phosphorus)
5 Orientation <111> ± 0.1°
6 Thickness 350 ± 10 µm
7 Resistivity 0.001 – 0.005 Ohm cm
8 Voids / Defects None
9 Carbon content 0.5PPMA
10 Oxygen content 28 ± 5 PPMA
11 Wafer Primary Flat SEMI STANDARD
12 Secondary Flat None
13 Total Thickness Variation (TTV) 10 µm (max)
14 Bow/ Warp 40 µm(max)
15 Taper 10 µm (max)
16 Radial resistivity variation in wafer 8 % (max.)
17 Dislocation 100/cm2 (max)
18 Finish Double Side Polished (DSP)
19 Appearance No Scratches, Haze should be visible under bright collimated light  (on both sides)
20 Edge exclusion ≤ 5 mm
21 Voids / Defects None
22 Packaging Should be vacuum-sealed in “Class 10” environment in double layer packing. Wafers should be shipped in Fluorware ORION TWO wafer shippers or equivalent makes made from ultra clean polypropylene
23 Certification Vendor to provide the certificate of conformance to the specifications for the product lots shipped.

 

2. Annealing Wafer Process

Annealed wafer formation is to place the polished wafer in a diffusion furnace. The high-purity hydrogen annealing wafer is to place the polished silicon wafer in a wafer annealing furnace/diffusion furnace. The silicon wafer is annealed in a hydrogen or argon atmosphere at a high temperature of 1100~1200°C. After a few hours, the oxygen in the surface layer of the wafer can be diffused outwards, which can greatly reduce the oxygen concentration in the surface layer and eliminate the tiny crystal originated particle (COP) defects formed during the crystal pulling process. In addition, the bulk micro defect (BMD) formed in the high-temperature heat treatment process can absorb the metal impurities that diffuse rapidly on the surface of the wafer, thereby having better crystal perfection, which can meet the higher semiconductor etching requirements, improving semiconductor IC process yield and product quality.

3. Industry Standards for Silicon Wafer Annealing

The standards is suitable for the silicon annealed wafer with the line width of 180nm, 130nm and 90nm, which is for manufacturing semiconductor devices and integrated circuit. The specific technical requirements of hydrogen / argon annealed wafer are as stipulated in the table:

Item 180 nm 130 nm 90 nm
Wafer State Before Annealing (Polishing Wafer)
1.0 Basic Characteristics
1.1 Growth Method CZ/MZ
1.2 Orientation <100>
1.3 Conductivity Type P
1.4 Dopant Boron
1.5 Edge Removal 3 mm 3 mm 2 mm
1.6 Other Dopants Nitrogen or carbon is determined by the supplier and the buyer
1.7 Surface Crystal Orientation Deviation 0.00°± 1.00°
2.0 Electrical Characteristics
2.1 Resistivity (Center Point) To be negotiated between the supplier and the demander
2.2 Radial Resistivity Variation ≤20%
3.0 Chemical Properties
3.1 Oxygen Content/Correction Factor To be negotiated by the buyer and supplier
3.2 Radial Oxygen Variations ±10% (Edge 10mm)
3.3 Carbon Content ≤0.5ppma
6.0 Geometric Size
6.1 Diameter 200 mm±0.2 mm 300 mm±0.2 mm 300 mm±0.2 mm
6.2 Edge Polishing Negotiated by the buyer and the supplier
6.3 Thickness 725 um±20 um
(c ut or reference surface)
775 um±20um 775 um±20 pm
6.4 TTV ≤10 um
7.0 Back Surface Characteristics
7.1 Chipping None
7.2 Brightness (Gloss) Not stipulated 0.80 (80% of front gloss) 0.80 (80% of front gloss)
7.3 Scratch (Macro) Total Length ≤0.25×diameter
8.0 Annealing conditions
8.1 Annealing Environment Hydrogen, argon or others

(To be negotiated between the supplier and the demander)

Hydrogen, argon or others

(To be negotiated between the supplier and the demander)

Hydrogen, argon or others

(To be negotiated between the supplier and the demander)

9.0 State of the Silicon Wafer after Annealing
9.1 Edge Surface Condition Corrosion or polishing (to be agreed between the supplier and the buyer)
10.0 Geometry of the Silicon Wafer after Annealing
10.1 Warp ≤75 um ≤100 um ≤100 um
10.2 Flatness SFQR≤180 nm SFQR≤130 nm SFQR≤90 nm
11.0 Surface Metal Content on the Front surface of the Silicon Wafer after Annealing
11.1 Sodium ≤1.3×1010cm-2 ≤1.3×1010cm-2 ≤1×1010 cm-2
11.2 Aluminum ≤1×1011 cm-2 ≤1×1011 cm-2 ≤1×1010 cm-2
11.3 Potassium ≤1.3×1010cm-2 ≤1.3×1010cm-2 ≤1×1010 cm-2
11.4 Chromium ≤1.3×1010cm-2 ≤1.3×1010cm-2 ≤1×1010 cm-2
11.5 Iron ≤1.3×1010cm-2 ≤1.3×1010cm-2 ≤1×1010 cm-2
11.6 Nickel ≤1.3×1010cm-2 ≤1.3×1010cm-2 ≤1×1010 cm-2
11.7 Copper ≤1.3×1010cm-2 ≤1.3×1010cm-2 ≤1×1010 cm-2
11.8 Zinc ≤1×1011 cm-2 ≤1×1011 cm-2 ≤1×1010 cm-2
11.9 Calcium ≤1.3×1010cm-2 ≤1.3×1010cm-2 ≤1×1010 cm-2
12.0 Inspection Items on the Front Side of the Annealed Silicon Wafer
12.1 Slip To be agreed between the supplier and the demander
12.2 Oxide Fault
12.3 Scratches None
12.4 Total length of scratch (micro) ≤0.25×diameter
12.5 Fog No fog under strong light
12.6 Total Local Light Scattering (overall LLS)/cm-2 [email protected]
120 nm LSE
[email protected]
90 nm LSE
[email protected]
90 nm LSE
12.7 Local Light Scattering (only COP)/cm2 To be agreed between the supplier and the demander
12.8 Other Front Surface Defects
13.0 Inspection of the Back Side of the Annealed Silicon Wafer
13.1 Contamination / Area To be negotiated by the supplier and the demander
13.2 Other Back Defects
14.0 Other Characteristics of Silicon Wafer Annealed
14.1 Iron Content To be negotiated by the supplier and the demander
14.2 BMD Etching Zone Depth
14.3 BMD Density
14.4 Others
Not stipulated: It means that no requirements are made for the item in this standard. If the customer has requirements for the item, the customer will give the specification.

 

Note: usually, the technical requirement for the thermally annealed silicon wafers produced by PAM-XIAMEN will be higher than that stipulated in the industry.

Generally, CMOS component manufacturing and DRAM manufacturers have strict requirements on the defects on the surface of the wafer. Therefore, the use of annealed wafer with low defect density (COP, OSF) can have a higher gate oxide breakdown voltage to increase product yield rate. In addition, processing polished wafer into annealing silicon wafer is relatively simple, so the unit price of annealing wafers is lower than that of epitaxial wafers, which can partially replace the demand for silicon thin film epitaxial wafers.

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For more information, please contact us email at [email protected] and [email protected].

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