2-28.WARP
Warp is the difference between the maximum and the minimum distances of the median surface of a free, un-clamped wafer from the reference plane defined above. This definition follows ASTM F657, and ASTM F1390,which deviation from a plane of a slice or wafer centerline containing both concave and convex regions.
3-6. Edge Chips Areas where material has been unintentionally removed from the wafer.Do not confuse fractures in epi crown with edge chips.
5-5 SiC Device Fundamentals To minimize the development and production costs of SiC electronics, it is important that SiC device fabrication takes advantage of existing silicon and GaAs wafer processing infrastructure as much as possible. As will be discussed in this section, most of the [...]
5-3-3 System Benefits of High-Power High-Temperature SiC Devices Uncooled operation of high-temperature and high-power SiC electronics would enable revolutionary improvements to aerospace systems. Replacement of hydraulic controls and auxiliary power units with distributed “smart” electromechanical controls capable of harsh ambient operation will enable substantial jet-aircraft weight savings, reduced [...]
2-11.Edge Chips Any edge anomalies (including wafer saw exit marks) in excess of 1.0 mm in either radial depth or width. As viewed under diffuse illumination, edge chips are determined as unintentionally missing material from the edge of the wafer.
2-15.Orange Peel Visually detectable surface roughening when viewed under diffuse illumination.
2-12.Edge Exclusion The outer annulus of the wafer is designated as wafer handling area and is excluded from surface nish criteria (such as scratches, pits, haze, contamination, craters,dimples, grooves, mounds, orange peel and saw marks). This annulus is 2 mm for 76.2 mm substrates, and [...]
