Knowledge

SiC Epilayers

Most SiC electronic devices are not fabricated directly in sublimation-grown wafers, but are instead fabricated in much higher quality epitaxial SiC layers that are grown on top of the initial sublimation grown wafer. Well-grown SiC epilayers have superior electrical properties and are more controllable and reproducible than bulk sublimation-grown [...]

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5-4-4-1 SiC Epitaxial Growth Processes

5-4-4-1 SiC Epitaxial Growth Processes An interesting variety of SiC epitaxial growth methodologies, ranging from liquid-phase epitaxy, molecular beam epitaxy, and chemical vapor deposition(CVD) have been investigated . The CVD growth technique is generally accepted as the most promising method for attaining epilayer reproducibility, quality, and throughputs required for mass [...]

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5-4-4-2 SiC Epitaxial Growth Polytype Control

5-4-4-2 SiC Epitaxial Growth Polytype Control Homoepitaxial growth, whereby the polytype of the SiC epilayer matches the polytype of the SiC substrate, is accomplished by “step-controlled” epitaxy . Step-controlled epitaxy is based upon growing epilayers on an SiC wafer polished at an angle (called the “tilt-angle” or “off-axis angle”) of [...]

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5-4-4-3 SiC Epilayer Doping

5-4-4-3 SiC Epilayer Doping In-situ doping during CVD epitaxial growth is primarily accomplished through the introduction of nitrogen (usually) for n-type and aluminum (usually trimethyl- or triethylaluminum) for p-type epilayers . Some alternative dopants such as phosphorus and boron have also been investigated for the n-and p-type epilayers, respectively . [...]

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5-4-5 SiC Crystal Dislocation Defects

5-4-5 SiC Crystal Dislocation Defects Table 5.2 summarizes the major known dislocation defects found in present-day commercial 4H- and 6H-SiC wafers and epilayers . Since the active regions of devices reside in epilayers, the epilayer defect content is clearly of primary importance to SiC device performance. However, as evidenced by [...]

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5-5 SiC Device Fundamentals

5-5 SiC Device Fundamentals To minimize the development and production costs of SiC electronics, it is important that SiC device fabrication takes advantage of existing silicon and GaAs wafer processing infrastructure as much as possible. As will be discussed in this section, most of the steps necessary to fabricate SiC [...]

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5-5-1 Choice of Polytype for Devices

5-5-1 Choice of Polytype for Devices As discussed in Section 4, 4H- and 6H-SiC are the far superior forms of semiconductor device quality SiC commercially available in mass-produced wafer form. Therefore, only 4H- and 6H-SiC device processing methods will be explicitly considered in the rest of this section. It should [...]

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5-5-2 SiC-Selective Doping: Ion Implantation

5-5-2 SiC-Selective Doping: Ion Implantation The fact that diffusion coefficients of most SiC dopants are negligibly small (at 1800°C) is excellent for maintaining device junction stability, because dopants do not undesirably diffuse as the device is operated long term at high temperatures. Unfortunately, this characteristic also largely (except for B at extreme temperatures [...]

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5-5-3 SiC Contacts and Interconnect

5-5-3 SiC Contacts and Interconnect All useful semiconductor electronics require conductive signal paths in and out of each device as well as conductive interconnects to carry signals between devices on the same chip and to external circuit elements that reside off-chip. While SiC itself is theoretically capable of fantastic electrical operation under extreme [...]

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5-5-4 Patterned Etching of SiC for Device Fabrication

5-5-4 Patterned Etching of SiC for Device Fabrication At room temperature, there are no known conventional wet chemicals that etch single-crystal SiC. Most patterned etching of SiC for electronic devices and circuits is accomplished using dry etching techniques. The reader should consult References 122–124 which contain summaries of dry SiC etching results obtained [...]

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