PAM-XIAMEN Offers High Purity Semi-Insulating SiC Substrate

PAM-XIAMEN Offers High Purity Semi-Insulating SiC Substrate

Xiamen Powerway Advanced Material Co.,Ltd., a leading supplier of High Purity Semi-insulating SiC substrate and other related products and services announced the new availability of size 2”&3”&4”&6” is on mass production by PVT. This new product represents a natural addition to PAM-XIAMEN’s product line. Dr. Shaka, said, “We are pleased to offer High Purity Semi-insulating SiC wafer to our customers. 4H Semi-insulating Silicon Carbide (SiC) substrate is available in on-axis orientation. From epitaxy process of semi-insulating silicon carbide wafers in our research, we found micropipe density normally is not main obstacle to grow high quality epi layers, instead, carbon inclusions because a problem, hence, we focus on control or remove wafer without or smaller carbon inclusions, so for research grade and production grade high purity Semi-insulating SiC substrate, it can ensure high quality heteroepitaxy such as AlGaN/GaN structure”.

1. High Purity Semi Insulating SiC Wafer List:

Item Number Diameter Type Orientation Thickness Resistivity(Ohm-cm) Grade
S4H-150-SI-PWAM-500-D 150mm HPSI On-axis 500µm +/-25µm ≥ 1E7 Dummy Grade
S4H-150-SI-PWAM-500-R 150mm HPSI On-axis 500µm +/-25µm ≥ 1E7 Research Grade
S4H-150-SI-PWAM-500-A 150mm HPSI On-axis 500µm +/-25µm ≥ 1E7 Production Grade
S4H-100-SI-PWAM-500-D 100mm HPSI On-axis 500µm +/-25µm ≥ 1E7 Dummy Grade
S4H-100-SI-PWAM-500-R 100mm HPSI On-axis 500µm +/-25µm ≥ 1E7 Research Grade
S4H-100-SI-PWAM-500-A 100mm HPSI On-axis 500µm +/-25µm ≥ 1E7 Production Grade
S4H-76-SI-PWAM-350-D 76.2mm HPSI On-axis 350µm +/-25µm ≥ 1E7 Dummy Grade
S4H-76-SI-PWAM-350-R 76.2mm HPSI On-axis 350µm +/-25µm ≥ 1E7 Research Grade
S4H-76-SI-PWAM-350-A 76.2mm HPSI On-axis 350µm +/-25µm ≥ 1E7 Production Grade
S4H-51-SI-PWAM-350-D 50.8mm HPSI On-axis 350µm +/-25µm ≥ 1E7 Dummy Grade
S4H-51-SI-PWAM-350-R 50.8mm HPSI On-axis 350µm +/-25µm ≥ 1E7 Research Grade
S4H-51-SI-PWAM-350-A 50.8mm HPSI On-axis 350µm +/-25µm ≥ 1E7 Production Grade

 

2. Specification of High Purity Semi-Insulating SiC Substrate

2-1 HIGH PURITY SEMI-INSULATING 4H-SIC WAFER SPECIFICATION,2”
SUBSTRATE PROPERTY S4H-51-SI-PWAM-350 
Description A/B Production Grade  C/D Research Grade  D Dummy Grade  4H SEMI Substrate
Polytype 4H
Diameter (50.8 ± 0.38) mm
Thickness  (350 ± 25) μm
Type High Purity Semi-Insulating(HPSI), undoped
Dopant Undoped
Resistivity (RT) >1E7 Ω·cm
Surface Roughness < 0.5 nm (Si-face CMP Epi-ready); <1 nm (C- face Optical polish)
FWHM A<30 arcsec                   B/C/D <50 arcsec
Micropipe Density A+≤1cm-2  A≤10cm-2   B≤30cm-2  C≤50cm-2  D≤100cm-2
Surface Orientation
On axis                         <0001>± 0.5°
Off axis                         3.5° toward <11-20>± 0.5°
Primary flat orientation Parallel {1-100} ± 5°
Primary flat length 16.00 ± 1.70 mm
Secondary flat orientation Si-face:90° cw. from orientation flat ± 5°
<span “=”” style=”font-size: 10pt;”>                       C-face:90° ccw. from orientation flat ± 5°
Secondary flat length 8.00 ± 1.70 mm
Surface Finish Single or double face polished
Packaging Single wafer box or multi wafer box
Usable area ≥ 90 %
Edge exclusion 1 mm

 

2-2 HIGH PURITY SEMI-INSULATING 4H-SIC SUBSTRATE SPECIFICATION,3”
SUBSTRATE PROPERTY S4H-76-N-PWAM-350         
Description A/B Production Grade  C/D Research Grade  D Dummy Grade   4H SiC Substrate
Polytype 4H
Diameter (76.2 ± 0.38) mm
Thickness      (350 ± 25) μm                       
Type High Purity Semi-Insulating(HPSI)
Dopant Undoped
Resistivity (RT) >1E7Ω·cm
Surface Roughness < 0.5 nm (Si-face CMP Epi-ready); <1 nm (C- face Optical polish)
FWHM A<30 arcsec                   B/C/D <50 arcsec
Micropipe Density A+≤1cm-2  A≤10cm-2   B≤30cm-2  C≤50cm-2  D≤100cm-2
TTV/Bow /Warp <25μm
Surface Orientation <0001>± 0.5°
Primary flat orientation <11-20>±5.0°
Primary flat length 22.22 mm±3.17mm
0.875″±0.125″
Secondary flat orientation Si-face:90° cw. from orientation flat ± 5°
Primary flat length C-face:90° ccw. from orientation flat ± 5°
Secondary flat length 11.00 ± 1.70 mm
Surface Finish Single or double face polished
Packaging Single wafer box or multi wafer box
Scratch None
Usable area ≥ 90 %
Edge exclusion 2mm

 

2-3 4H HIGH PURITY SEMI-INSULATING SIC WAFER SPECIFICATION,4”
SUBSTRAIE PROPERTY A Grade B Grade C Grade
Diameter 100.0 mm + 0.0/-0.5 mm
Surface orientation {0001} ± 0.2°
Primary flat orientation [11-20] ± 5°
Secondary flat orientation Silicon face up: 90° CW. from Prime flat ±5.0°
Primary flat length 32.5 mm ± 2.0 mm
Secondary flat length 18.0 mm ± 2.0 mm
Surface Roughness Si-face Ra≤0.2 nm
Thickness 500.0μm ± 25.0μm
TTV ≤10μm
C10mm’LrV C10mm’ ≤3μm ≤5μm
Warp ≤35μm ≤45μm
Bow(Absolute) ≤25μm ≤30μm
Micropipe Density ≤1 cm-2 ≤10 cm-2 ≤20 cm-2
Resistivity ≥1E8Ω-cm 75% area: ≥1E8Ω-cm
Polytype None permitted Cumulative area≤5%
Hex Plates by high intensity light None permitted Qty.6<100μm Cumulative area≤5%
Visual Carbon Inclusions Cumulative area≤0.05% Cumulative area≤10% N/A
Surface finish Double Side Polish, Si Face CMP (chemical polishing)
Wafer edge Bevelling
Edge chips/indents by diffuse lighting None permitted≥0.5mm width and depth Qty.2 <1.0 mm width and depth
Scratches(CS920/CS8520) Cumulative length≤1*wafer diameter Cumulative length≤1.5*wafer diameter
Cracks None permitted
Edge exclusion 3mm

 

2-4 4H HIGH PURITY SEMI-INSULATING SIC SUBSTRATE SPECIFICATION,6”
SUBSTRATE PROPERTY A Grade B Grade C Grade
Diameter 150.0 mm ± 0.2 mm
Surface orientation {0001} ± 0.2°
Notch orientation [1-100] ± 5.0°
Notch depth 1.0 mm +0.25 mm, -0.00 mm
Surface Roughness Si-face Ra≤0.2 nm
Thickness 500.0μm ± 25.0μm
TTV ≤10μm
LTV(10mm2) ≤3μm ≤5μm
Warp ≤40μm ≤60μm
Bow(Absolute) ≤25μm ≤40μm
Micropipe Density ≤1 cm-2 ≤5 cm-2 ≤10 cm-2
Resistivity ≥1E8Ω-cm 75% area: ≥1E8Ω-cm
Polytype None permitted Cumulative area≤5%
Hex Plates by high intensity light Cumulative area ≤0.05% Cumulative area ≤0.1% Cumulative area≤5%
Visual Carbon Inclusions Cumulative area ≤0.05% Cumulative area ≤10% N/A
Surface finish Double Side Polish, Si Face CMP(chemical polishing)
Wafer edge Bevelling
Edge chips/indents by diffuse lighting None permitted ≥0.5mm width and depth Qty.2 <1.0 mm width and depth
Scratches(CS920/CS8520) Cumulative length≤1*wafer diameter Cumulative length≤1.5*wafer diameter
Cracks None permitted
Edge exclusion 3mm

3. Fluorescence PL Diagram of Vsi

See below Fluorescence PL diagram of Vsi, tested by a 2inch,4H, high purity semi insulating SiC substrate.

Fluorescence PL diagram of Vsi

Fluorescence PL diagram of Vsi

In the high purity semi-insulating SiC substrate market, the current mainstream silicon carbide substrate product specification is 4 inches. Because of high purity without any dopants, the HPSI SiC substrate material keep high resistivity with good uniformity. Semi-insulating SiC substrate is mainly used in the manufacture of gallium nitride radio frequency devices. By growing a gallium nitride epitaxial layer on a SiC wafer of HPSI type, a SiC-based gallium nitride epitaxial wafer is prepared, which can be further made into a GaN RF device.

For more information, please contact us email at [email protected] and [email protected].

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