3-4. Step Bunching
Step bunching is visible as a pattern of parallel lines running perpendicular to the major at. If present, estimate the % of speci ed area affected.
3-4. Step Bunching
Step bunching is visible as a pattern of parallel lines running perpendicular to the major at. If present, estimate the % of speci ed area affected.
1-1.lattice parameter The lattice constant, or lattice parameter, refers to the constant distance between unit cells in a crystal lattice. Lattices in three dimensions generally have three lattice constants, referred to as a, b, and c. However, in the special case of cubic crystal structures, [...]
2-12.Edge Exclusion The outer annulus of the wafer is designated as wafer handling area and is excluded from surface nish criteria (such as scratches, pits, haze, contamination, craters,dimples, grooves, mounds, orange peel and saw marks). This annulus is 2 mm for 76.2 mm substrates, and [...]
3-2. Scratches Grooves or cuts below the surface plane of the wafer having a length-to-width ratio of greater than 5 to 1. Scratches are speci ed by the number of discrete scratches times the total length in fractional diameter.
5-3-2 High-Power Device Operation The high breakdown field and high thermal conductivity of SiC coupled with high operational junction temperatures theoretically permit extremely high-power densities and efficiencies to be realized in SiC devices. The high breakdown field of SiC relative to silicon enables the blocking voltage region [...]
3-1. Large Point Defects Defects which exhibit a clear shape to the unassisted eye and are > 50 microns across. These features include spikes, adherent particles, chips and craters. Large point defects less than 3 mm apart count as one defect.
2-8.Secondary Flat Orientation A at of shorter length than the primary orientation at,whose position with respect to the primary orientation at identies the face of the wafer.
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