2-4.Wafer Surface Orientation
Denotes the orientation of the surface of a wafer with respect to a crystallographic plane within the lattice structure.
In wafers cut intentionally “off orientation”, the direction of cut is parallel to the primary at, away from the secondary at.
Measured with [...]
2018-06-28meta-author
5-3-1 High-Temperature Device Operation
The wide bandgap energy and low intrinsic carrier concentration of SiC allow SiC to maintain
semiconductor behavior at much higher temperatures than silicon, which in turn permits SiC semiconductor
device functionality at much higher temperatures than silicon . As discussed in basic
semiconductor electronic [...]
2018-06-28meta-author
2-18.Grain boundaries
They are interfaces where crystals of different orientations meet. A grain boundary is a single-phase interface, with crystals on each side of the boundary being identical except in orientation. The term “crystallite boundary” is sometimes, though rarely, used. Grain boundary areas contain those [...]
2018-06-28meta-author
5-5-1 Choice of Polytype for Devices
As discussed in Section 4, 4H- and 6H-SiC are the far superior forms of semiconductor device quality SiC commercially available in mass-produced wafer form. Therefore, only 4H- and 6H-SiC device processing methods will be explicitly considered in the rest [...]
2018-06-28meta-author
3-6. Edge Chips
Areas where material has been unintentionally removed from the wafer.Do not confuse fractures in epi crown with edge chips.
2018-06-28meta-author
2-12.Edge Exclusion
The outer annulus of the wafer is designated as wafer handling area and is excluded from surface nish criteria (such as scratches, pits, haze, contamination, craters,dimples, grooves, mounds, orange peel and saw marks). This annulus is 2 mm for 76.2 mm substrates, and [...]
2018-06-28meta-author