Silicon Wafer Flatness Measurement – Criterion

Silicon Wafer Flatness Measurement – Criterion

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The purity, surface flatness, cleanliness and impurity contamination of semiconductor silicon wafers have an extremely important influence on the chips. The local flatness of silicon wafer is one of the important parameters that directly affects the quality, yield and reliability of process line widths such as integrated circuit lithography. Silicon wafer flatness is a surface property, expressed in um, which refers to the difference between the highest point and the lowest point between the wafer surface and the reference plane.

There are four commonly used methods for silicon wafer flatness measurement: acoustic method, interferometry method, capacitance method and laser beam reflection method. All of the methods are non-contact, in order to reduce damage and contamination on the surface of silicon wafers. Take the capacitance method for example:

Standard Method for Measuring Polished Wafer Flatness –Capacitive Displacement Sensor

1. Applicability of Capacitive Displacement Sensor for Silicon Wafer Flatness Inspection

A method of capacitive displacement sensors is suitable for measuring the polished silicon wafer flatness tolerance. The cutting wafers, grinding wafers, and etching wafers can also refer to this method.

This method is suitable for measuring the surface flatness of silicon polished wafers with standard diameters of 76 mm, 100 mm, 125 mm, 150 mm, 200 mm, resistivity not greater than 200 Ω•cm and thickness not greater than 1000 um and intuitive description of the surface of silicon wafers outline shape.

2. Capacitive Displacement Sensor Measuring Silicon Wafer Flatness

Put the silicon wafer flat between a pair of coaxially opposed capacitive displacement sensors (probes for short), apply a high-frequency voltage to the probes, and a high-frequency electric field is formed between the silicon wafer and the probe, and a capacitor is formed between them. The circuit in the probe measures the amount of current change during the period, and the capacitance value C can be measured. As shown in Figure 1. C is given by equation (1):

Figure 1 Schematic Diagram of Capacitive Displacement Sensor for Measuring Silicon Wafer Flatness

D – distance between A and B probes;

a – the distance between the A probe and the upper surface;

b – the distance between the B probe and the lower surface;

t – silicon wafer thickness.

Figure 1 Schematic Diagram of Capacitive Displacement Sensor for Measuring Silicon Wafer Flatness

In the formula:

C – the total capacitance measured between the upper and lower probes and the wafer surface, in Farads (F);

K – free space permittivity in Farads per meter F/m;

A – the surface area of the probe, in square meters (m2);

a – the distance between the A probe and the upper surface, in meters (m);

b – the distance between the B probe and the lower surface, in meters (m);

C0 – Parasitic capacitance mainly due to probe structure, in Farads (F)

Since the distance D between the two probes and the distance b from the lower probe to the lower surface have been fixed during calibration, the capacitance value C measured by the instrument is calculated according to formula (1), and a can be obtained, thereby calculating wafer surface flatness and other geometric parameters. Choose the appropriate reference plane and focal plane to calculate the required parameters.

3. How to Determine Wafer Flatness by Capacitive Displacement Sensor?

3.1 Select Qualified Quality Area (FQA) of Silicon Wafer

The edge of 3 mm of silicon wafer is not included in the qualified quality area. If there are special silicon wafer flatness requirements, it can be selected according to the agreed value between the supplier and the buyer.

3.2 Select Silicon Wafer Flatness Parameter

Select the reference surface – Front (F) or Back (B)

Select a reference plane from the following:

a) ideal back plane (I);

b) Front three-point plane (3);

c) Frontal least squares plane (L).

3.3 Select Measurement Parameters

TIR – Total Indication Reading

FPD – Focal Plane Deviation

4. How to Calculate Silicon Wafer Flatness Data?

The reference plane is described by the following form:

Ideal back surface reference plane:

Least Squares Reference Surface:

Choose aR, bR, cR to satisfy (4) as the minimum value.

Three-point reference plane:

In the formula: x1, y1; x2, y2; x3, y3 are evenly distributed on the circumference 3mm from the edge of the silicon wafer.

The focal plane is described by:

The focal plane is parallel to the reference plane, and the focal plane is considered to be the same as the reference plane when calculating the flatness, so

aF=aR

bF=bR

cF=cR

The difference between the thickness of each point of the specimen and the reference or focal plane is described by the following form:

In the formula:

i – can be R or F;

x, y – should be within FQA

TIR is calculated as follows:

FPD is calculated as follows:

* The single-laboratory precision of this method: FPD is not greater than 0.21 um (R3S);

                                                                             TIR is not greater than 0.27 um (R3S).

* Multi-laboratory precision of this method: FPD is not greater than 0.48 um(R3S);

                                                                    TIR is not greater than 0.54 um(R3S).

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