Highlights
•Fabrication scheme for heterogenous Si-to-InP circuits on wafer level is described.
•Wafer-to-wafer alignment accuracy better than 4–8 μm after bonding obtained.
•Interconnects with excellent performance up to 220 GHz demonstrated.
•Palladium barrier necessary when combining Al-based technology with gold based one.
Abstract
In order to benefit from the material [...]
GaN LED structure grown on nano-scale patterned sapphire (Al2O3) substrate can be provided with high efficiency of photoluminescence and electroluminescence. However, because of the high customization of the epitaxial process in the InGaN/GaN-quantum wells based LED heterostructure, we cannot get the optimal solution for [...]
2022-01-06meta-author
PAM-XIAMEN can provide a series products of terahertz chip: Power Amplifier (PA) Chip, Low Noise Amplifier (LNA) Chip, PIN/FET Switch, Zero Bias Detector Chip, Amplification Frequency Multiplication Chain (AMC) Chip, MIXER Chip, Schottky Frequency Multiplication MMIC, Schottky Mixing MMIC, and Attenuator Chip. The terahertz chip is a brand-new microchip, a [...]
2021-07-16meta-author
The effect of anisotropy on the deformation and fracture of sapphire wafers subjected to thermal shocks
This paper studies the effect of anisotropy on the response of an R -plane sapphire wafer to a rapid thermal loading. The finite element method was used to analyse the [...]
Single crystal 6H-SiC MEMS fabrication based on smart-cut technique
A new single crystal silicon carbide (SiC) MEMS fabrication process is developed using a proton-implantation smart-cut technique. A 6H-SiC layer with 1.3 µm thickness has been achieved over an oxidized silicon substrate using the proposed technique. [...]
2018-08-22meta-author
PAM XIAMEN offers 4″ Silicon Wafer.
Material
Orient.
Diam.
Thck
(μm)
Surf.
Resistivity
Ωcm
Comment
n-type Si:As
[111-4°] ±0.5°
4″
325
P/E
0.001-0.005
SEMI Prime, Back Surface: Sand blasted with LTO seal
n-type Si:As
[111-4°] ±0.5°
4″
300
P/E
0.001-0.005
SEMI Prime, Back-side Sand-blasted with LTO seal, in Empak cassettes of 7 wafers
n-type Si:As
[111-2°] ±0.5°
4″
400
P/EOx
0.001-0.004 {0.0018-0.0036}
SEMI Prime, Epi edges, 0.5μm LTO
n-type Si:As
[111-4°] ±0.5°
4″
525
P/E
0.001-0.005
SEMI Prime
n-type Si:As
[111-4°]
4″
525
P/E
0.001-0.005
SEMI Prime
n-type Si:As
[111] ±0.5°
4″
1000
P/E
0.001-0.005 {0.0031-0.0040}
SEMI Prime, TTV<4μm, [...]
2019-03-05meta-author
