2-12.Edge Exclusion
The outer annulus of the wafer is designated as wafer handling area and is excluded from surface nish criteria (such as scratches, pits, haze, contamination, craters,dimples, grooves, mounds, orange peel and saw marks). This annulus is 2 mm for 76.2 mm substrates, and [...]
2018-06-28meta-author
5-5-5 SiC Insulators: Thermal Oxides and MOS Technology
The vast majority of semiconductor-integrated circuit chips in use today rely on silicon metal-oxide–
semiconductor field-effect transistors (MOSFETs), whose electronic advantages and operational
device physics are summarized in Katsumata’s chapter and elsewhere . Given the extreme
usefulness and success of [...]
2018-06-28meta-author
3-4. Step Bunching
Step bunching is visible as a pattern of parallel lines running perpendicular to the major at. If present, estimate the % of speci ed area affected.
2018-06-28meta-author
2-22.Surface Roughness
Often shortened to roughness, is a measure of the texture of a surface. It is quantified by the vertical deviations of a real surface from its ideal form. If these deviations are large, the surface is rough; if they are small the surface [...]
2018-06-28meta-author
1-3.Mohs Hardness
Rough measure of the resistance of a smooth surface to scratching or abrasion, expressed in terms of a scale devised(1812)by the German mineralogist Friedrich Mohs. The Mohs hardness of a mineral is determined by observing whether its surface is scratched by a substance [...]
2018-06-28meta-author
2-9.(Area) Wafer Contamination
Any foreign matter on the surface in localized areas which is revealed under high intensity (or diffuse) illumination as discolored, mottled, or cloudy appearance resulting from smudges, stains or water spots.
2018-06-28meta-author