150mm 4H n-type SiC epi wafer with excellent uniformity and extremely low defect density is available. SiC epitaxial wafer refers to a silicon carbide wafer on which a single crystal film (epitaxial layer) with certain requirements and the same crystal as the substrate is grown on a silicon carbide substrate. now please see below SiC Epilayer on SiC substrates example:
1. Specifications of 150mm 4H N-type SiC Epi Wafer
1.1 ITEM: PAM-191014-SIC-EPI
| SiC wafers (research/production grade) | |
| Substrate Thickness (Average) [μm] | 350±25 |
| Diameter [mm] | 150 ± 0.25 |
| Flat length [mm] | 47.5 ± 2.0 |
| Poly-type/Conductivity | 4H/n.type |
| Front Surface Finish | CMP |
| Epi-face/Orientation | Si/(0001) 4± 0.5° off |
| Substrate Resistivity [Ω.cm] | ≤ 0.025 |
| Micropipe Density (MPD) [cm-2] | ≤ 1.00 |
| Basal plane defect (BPD) [cm-2] | ≤ TBC |
| Total Stacking Fault (TSD) [cm-2] | ≤ TBC |
| 1st EPI Thickness [μm] | 1 |
| 1st EPI Carrier Conc. [E18 cm-3] | 1 |
| 2nd EPI Thickness 9 point Average [μm] | 5~10.00 ± 10% |
| 2nd EPI Carrier Conc. 9 point Average [E16 cm-3] | 1.000 ± 0.20 |
| TTV [GBIR] [μm] | ≤ 15.00 |
| WARP (3p) [μm] | ≤ 60.00 |
| BOW (3p) [μm] | ± 40.00 |
| Edge exclusion | 1mm |
| EPI surface defect (PDD) [cm-2] | ≤ 2.00 |
| EPI surface roughness [nm] | ≤ 2.00 |
| Edge chips by diffuse lighting (max) | None |
| Cracks by high intensity light | None |
| Visual carbon Inclusions cumulative area | ≤ 0.05% |
| Scratches by high intensity light | None |
| Contamination by high intensity light | None |
1.2 ITEM: PAM-190919-SIC-EPI
| SiC wafers (research/production grade) | |
| Substrate Thickness (Average) [μm] | 150 ± 0.25 |
| Diameter [mm] | 350±25 |
| Flat length [mm] | 47.5 ± 2.0 |
| Poly-type/Conductivity | 4H/n.type |
| Front Surface Finish | CMP |
| Epi-face/Orientation | 4 degree off-axis |
| Substrate Resistivity [Ω.cm] | 0.015-0.028 |
| Micropipe Density (MPD) [cm-2] | <0.5 |
| Basal plane defect (BPD) [cm-2] | ≤ TBC |
| Total Stacking Fault (TSD) [cm-2] | ≤ TBC |
| 1st EPI Thickness [μm] | 0.5 |
| 1st EPI Carrier Conc. [E18 cm-3] | 1.00E+18 |
| 2nd EPI Thickness 9 point Average [μm] | 14 |
| Thickness Uniformity(%) | <3% |
| 2nd EPI Carrier Conc. 9 point Average [E15 cm-3] | 5.50E+15 |
| Thickness Uniformity(%) | <5% |
| TTV [GBIR] [μm] | – |
| WARP (3p) [μm] | ≤ 35 |
| BOW (3p) [μm] | – |
| Edge exclusion | 1mm |
| EPI surface defect (PDD) [cm-2] | – |
| EPI surface roughness [nm] | ≤ 2.00 |
| Edge chips by diffuse lighting (max) | None |
| Cracks by high intensity light | None |
| Visual carbon Inclusions cumulative area | – |
| Scratches by high intensity light | None |
| Contamination by high intensity light | None |
2. Current Situation of 150mm 4H N-type SiC Epi Wafer
The industry chain using silicon carbide materials as substrates mainly includes the preparation of silicon carbide substrate materials, the SiC epitaxy growth, device manufacturing and downstream application markets. On the SiC substrate, the chemical vapor deposition method (CVD method) is mainly used to generate the required thin sic epitaxial film on the surface of the substrate, forming an epitaxial wafer, and further make the device.
In practical applications, the requirements for the quality of the SiC epitaxial layer are very high. With the continuous improvement of pressure resistance, the thickness of the required SiC epi growth will be thicker, and the SiC epitaxy process cost will be adjusted accordingly. 150mm 4H N-type SiC epi wafer can meet the development of SiC power electronic devices with voltage levels of 3.3kV and below. However, it is still unable to meet the needs for the development of 10kV and above voltage level devices and the development of bipolar devices.
For more information, please contact us email at [email protected] and [email protected].