MOS vs SBD Grade SiC Substrate
Silicon carbide (SiC), as a representative third-generation semiconductor material, offers exceptional properties including a wide bandgap (3.26eV for 4H-SiC), high critical breakdown electric field (~2.5MV/cm), and high thermal conductivity (4.9W/cm·K), making it uniquely advantageous in high‑voltage, high‑frequency, and high‑temperature power electronics. However, the performance and reliability of SiC power devices are largely governed by the crystalline quality of the substrate material.
Commercial 6‑inch N‑type 4H‑SiC substrates are typically classified into P‑MOS grade and P‑SBD grade. Both grades share the same resistivity and polytype, yet differ critically in defect control standards – with MOS‑grade specifications being uniformly more stringent than SBD‑grade. Is this difference a genuine quality advantage, or merely a reflection of disparate testing criteria? For researchers, clarifying the underlying physical rationale is the prerequisite for correct substrate selection.
This article provides a systematic, professional analysis for academic researchers across three dimensions: quantitative defect specifications, the mechanisms by which defects affect device performance, and cost‑industry realities.
1. Specification Comparison: Key Quality Metrics for MOS‑Grade vs. SBD‑Grade SiC Substrates
The differences between P‑MOS and P‑SBD grade substrates are not found in basic parameters such as polytype or resistivity – both are 4H‑polytype, with resistivities in the range of 0.015–0.025 Ω·cm. The real distinction lies in the density control of various crystalline defects. Taking a 6‑inch SiC substrate as an example:
| Product | 6‑inch Silicon Carbide Substrate | |
| Grade | P‑MOS Grade | P‑SBD Grade |
| Polytype | 4H | |
| Resistivity | 0.015–0.025ohm·cm | |
| Micropipe Density (MPD) | ≤0.2/cm² | ≤0.5/cm² |
| Total Dislocation Density (EPD) | ≤4000/cm² | ≤8000/cm² |
| Threading Edge Dislocation (TED) | ≤3000/cm² | ≤6000/cm² |
| Basal Plane Dislocation (BPD) | ≤1000/cm² | ≤2000/cm² |
| Threading Screw Dislocation (TSD) | ≤600/cm² | ≤1000/cm² |
| Stacking Fault Area | ≤0.5% | ≤1% |
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The above comparison clearly shows that P‑MOS grade substrates enforce quality standards 1.7 to 2.5 times stricter than P‑SBD grade across all key defect metrics – micropipes, dislocations (EPD/TED/BPD/TSD), and stacking faults. These differences are not arbitrary “tiering” but are rooted in device physics: the channel region of a MOSFET is extremely sensitive to substrate defects, necessitating a near‑“zero‑defect” substrate, whereas SBDs have relatively higher tolerance.
2. Why Do MOSFETs Have Higher Requirements for SiC Substrate Quality?
2.1 Fundamental Differences in Device Structure
The disparity in defect tolerance between MOSFETs (Metal‑Oxide‑Semiconductor Field‑Effect Transistors) and SBDs (Schottky Barrier Diodes) originates from their fundamentally different operating principles.
An SBD is a two‑terminal device whose core is the Schottky barrier formed at the metal‑semiconductor interface. Current transport occurs primarily near the metal‑semiconductor junction and is relatively insensitive to deep‑bulk substrate defects. Even with a moderate density of dislocations in the substrate, as long as they do not directly affect the barrier region, the device can still function adequately.
A MOSFET, by contrast, is a three‑terminal device whose core functionality relies on a conductive channel situated between two P‑well regions. This channel carries the entire current during the on‑state, and its integrity directly determines the MOSFET’s transfer characteristics. Channel formation requires precise gate‑voltage modulation of carrier concentration at the SiC/SiO₂ interface, demanding exceptionally high crystalline perfection and interfacial uniformity from the substrate. Any substrate defect – particularly dislocations that propagate through the epilayer – can directly disrupt the electric‑field distribution and carrier transport properties within the channel region.
Fig. 1 Cross‑sectional schematics of (a) 4H‑SiC Schottky barrier diode (SBD) and (b) MOS capacitor (MOSC)
2.2 Specific Effects of Various Defects on MOSFET Performance
(1) Micropipes – The Most Lethal Defect
Micropipes are hollow core dislocations in SiC crystals and are extremely harmful defects. Research has long established that micropipes significantly reduce device breakdown voltage due to their hollow core structure. Each micropipe can act as a local electric‑field concentration point, causing premature breakdown at biases far below the designed voltage. For MOSFETs that must withstand high blocking voltages, the presence of micropipes is nearly unacceptable. This is precisely why MOS‑grade substrates enforce a micropipe density of ≤0.2/cm², while SBD‑grade allows up to 0.5/cm² – a difference that may seem small but has significant implications for yield in large‑area power chips.
(2) Dislocations – Threats to Breakdown Voltage and Reliability
Dislocations are the most common crystalline defects in SiC substrates, primarily comprising threading screw dislocations (TSD), threading edge dislocations (TED), and basal plane dislocations (BPD). Studies indicate that dislocation defects in SiC wafers pose a risk to MOSFET breakdown voltage. In MOSFETs, dislocations can introduce additional recombination centers or leakage paths in the channel region, leading to reduced breakdown voltage and increased off‑state leakage current.
Basal plane dislocations (BPDs) deserve particular attention – they have been identified as the root cause of bipolar degradation in SiC MOSFET body diodes. During body‑diode conduction, electron‑hole recombination triggers the expansion of stacking faults from BPDs, forming stacking faults in the drift region, which increases the body‑diode forward voltage drop and on‑resistance. This degradation occurs during long‑term device operation and represents one of the most critical reliability concerns for SiC MOSFETs.
In contrast, SBDs are less sensitive to dislocations. Hatakeyama et al. reported that if the epilayer defect density is sufficiently low – with dislocation densities on the order of 10000 cm⁻² – long‑term reliability of the MOSFET gate oxide under 3MV/cm electric field can be assured. This explains why SBD‑grade substrates permit higher dislocation densities (EPD ≤8000/cm²), while MOS‑grade requires control at ≤4000/cm².
Fig. 2 Influence of SiC epilayer defect density on gate oxide electric field strength
(3) Stacking Faults – Direct Threat to Epilayer Quality
The stacking faults in the substrate will penetrate into the epitaxial layer to form stripe layer faults (BSF), directly affecting the quality of the epitaxial layer. The epitaxial layer is the region where the MOSFET channel and drift region are located, and its quality directly determines the electrical performance of the device. The MOS level substrate controls the stacking fault area to ≤0.5%, while the SBD level relaxes it to ≤1%.
Chu et al. (2022) further provided experimental evidence at the device level: using a simple SBD structure to evaluate the quality of epitaxial layers, it was found that the SBD yield loss of epitaxial layers on high defect density wafers was as high as 45%, while that of low defect samples was only 17%, and there were significant differences in leakage current distribution between the two; However, the yield loss of MOS capacitors is not significantly correlated with defect density and is not suitable for substrate quality evaluation.
Fig. 3 Cumulative distributions of reverse leakage current for epitaxial SBDs at different reverse biases: (a) –5V, (b) –10V, (c) –15V, (d) –20V
For SiC device developers, understanding this physical logic is crucial: substrate selection is not simply about choosing “better” or “cheaper” – it is about precise matching based on device structure and experimental objectives.
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References:
- Fukuda, K., Kinoshita, A., Ohyanagi, T., Kosugi, R., Sakata, T., Sakuma, Y., … & Arai, K. (2010, July). Influence of processing and of material defects on the electrical characteristics of SiC-SBDs and SiC-MOSFETs. In Materials science forum (Vol. 645, pp. 655-660). Trans Tech Publications Ltd.
- Chu, K. W., Tseng, C. W., Tsui, B. Y., Wu, Y. C. S., Yang, C. J., & Hsu, C. (2022, March). An Evaluation for Quality Inspection of Epitaxial Layer and Heavily-doped 4H-SiC Substrate by Simple Schottky Barrier Diode and MOS Capacitor. In 2022 IEEE 34th International Conference on Microelectronic Test Structures (ICMTS) (pp. 1-4). IEEE.