4H-SiC Substrate Etch Morphology Control +

PAM-XIAMEN offers low defect 4H‑SiC substrates in the following specifications for universities and research institutes. For inquiries, please contact us at [email protected]

Parameter	Specification Range
Polytype	4H‑SiC
Diameter	2‑inch, 4‑inch, 6‑inch, 8‑inch
Orientation	On‑axis, off‑axis
Conductivity type	Semi‑insulating (V), N‑type(N), P-type(Al)
Surface finish	SSP, DSP

 

Silicon carbide (SiC) is a representative third‑generation semiconductor material, featuring a wide bandgap, high critical breakdown field, high thermal conductivity, and high saturated electron drift velocity. It is widely used in power electronics, RF devices, and MEMS sensors. Among its polytypes, 4H‑SiC is the most mature and has achieved large‑scale commercial supply of 4H‑SiC substrates.

In the quality characterization of 4H‑SiC substrates and epilayers, molten potassium hydroxide (KOH) etching is a common method for dislocation density statistics. The principle is based on the higher strain energy and stronger chemical activity at dislocation cores, which are preferentially attacked in the molten alkali, forming characteristic etch pits corresponding to dislocation types. However, actual etching results show that pits formed on different crystal faces (Si‑face and C‑face) and for different dislocation types exhibit significant differences in shape and size, thereby affecting the accuracy of dislocation classification and device performance evaluation. This is particularly critical for MEMS devices such as pressure sensors, where the surface roughness and stress concentration introduced by etch pits directly influence device performance.

Based on experimental studies of molten KOH etching of 4H‑SiC, this article systematically analyzes the physicochemical origins of etch‑pit shape differences, evaluates their differentiated impacts on power devices and pressure sensors, and proposes strategies for improving post‑etch morphology, providing a reference for related research.

1. Formation Mechanisms of Etch‑Pit Shape Differences

1.1 SiC Surface Polarity Leads to Anisotropic Etching Behavior

The (0001) Si‑face and (000‑1) C‑face of 4H‑SiC exhibit different etching characteristics in molten KOH. On the Si‑face, anisotropic preferential etching occurs, forming hexagonal pits at dislocations; on the C‑face, isotropic corrosion tends to dominate, producing a smoother surface with circular or shallow pits. Activation energy measurements show that the etching activation energy is 35.75 kcal/mol on the Si‑face and 25.09 kcal/mol on the C‑face, with the C‑face etching rate significantly higher than that of the Si‑face. First‑principles calculations indicate that the (1×1) reconstructed surface energy of the C‑face is lower than the (3×3) reconstructed Si‑face, but after oxidation the C‑face surface becomes unstable; the oxides are more readily removed by KOH, leading to uniform corrosion dominating.

1.2 Dislocation Type Affects Pit Geometry

Different dislocation types correspond to distinct etch‑pit features:

• Micropipe: large hexagonal deep pits;
• Threading screw dislocation (TSD): hexagonal sharp‑bottomed pits on the Si‑face, and raised hillocks on the C‑face;
• Threading mixed dislocation (TMD): hexagonal but with overlapping morphology with TSD and TED;
• Threading edge dislocation (TED): smaller hexagonal or circular shallow pits;
• Basal plane dislocation (BPD): elliptical or shell‑shaped pits.

Synchrotron X‑ray topography (SXRT) combined with etching confirms that on the Si‑face the pit shapes of TSD and TED are easily confused, whereas on the C‑face the hillocks formed from TSD after etching correspond one‑to‑one with SXRT results, facilitating accurate statistics.

Fig. 1 Comparison of synchrotron X‑ray topography (SXRT) and molten KOH selective etching for dislocations on the 4H‑SiC (0001) Si‑face

1.3 Oxidation‑Removal Cyclic Mechanism

The etching process proceeds via a cycle of two steps: oxidation of the SiC surface by dissolved oxygen and removal of the oxides by molten KOH. The C‑face has a much higher surface C=O/C–O fraction (16.31%) than the Si‑face (4.8%), making it more readily decomposed after oxidation, so that uniform corrosion prevails over dislocation‑preferential etching, resulting in shallow and round pits.

2. Differentiated Impacts of Etch Pits on Device Performance

2.1 Power Devices: Etch Pits Do Not Constitute a Failure Factor

In the manufacturing flow of power devices (e.g., MOSFETs, JBS diodes), molten KOH etching is used only for dislocation density inspection and is not retained in the final device structure. The influence of dislocations on leakage current originates from their electrical activity rather than surface morphology. Epitaxial growth can filter out most substrate dislocations, and device design can tolerate a certain density of dislocations without significantly affecting breakdown voltage and on‑resistance. Therefore, the shape of etch pits itself does not affect the final performance of power devices.

2.2 Pressure Sensors: Etch Pits Reduce Performance Reliability

The sensitive structures of pressure sensors (such as diaphragms and piezoresistors) are directly fabricated on the substrate or epilayer. The effects introduced by etch pits include:

• Stress concentration: sharp‑bottomed hexagonal pits generate local stress singularities under pressure, leading to increased nonlinearity in piezoresistive output and even crack initiation;
• Surface roughness: uniform etching on the C‑face increases surface roughness, degrading the precision of initial gap control in capacitive sensors;
• Pit coalescence: over‑etching causes adjacent pits to connect, forming micro‑trenches that compromise diaphragm integrity.

These factors directly affect the sensitivity, linearity, and long‑term stability of pressure sensors.

3. Process Strategies for Improving Etch Morphology

3.1 Optimizing the Etching Temperature and Time Window

For the Si‑face, there exists an optimal time window (2–6 minutes); beyond this, pits coalesce and the surface becomes rough. As the temperature is raised from 465°C, the overall etch rate increases but the selectivity decreases, blurring the pit boundaries. Recommendations:

• Si‑face dislocation revelation: 465–480°C, 2–5 minutes;
• C‑face etching: shorten the time to 1–2 minutes to avoid excessive hillock growth.

Fig. 2 Effect of temperature on total etch rate and selectivity during molten KOH etching of 4H‑SiC: (left) total etch rate; (right) optical micrographs of Si‑face dislocation etch pits at different etching temperatures

Fig. 3 Variation of micropipe pit diameter with molten KOH etching time on the Si‑face and C‑face of 4H‑SiC (480°C)

3.2 Single‑Side Protected Etching Method

Yang et al. employed a stack of two substrates back‑to‑back wrapped with nickel wire, exposing the outer surfaces as the Si‑face and C‑face respectively while protecting the inner surfaces. This method allows independent control of etching time on each side and is suitable for preparing pressure‑sensor substrates that require single‑side flatness.

3.3 Post‑Etching Treatment

For pressure‑sensor substrates, it is recommended to add a short chemical mechanical polishing (CMP) step or a low‑concentration HF cleaning after KOH etching to remove surface oxides and micro‑roughness. Alternatively, a “etch‑first, then light‑polish” sequence can be adopted: first complete the dislocation density inspection, then remove the surface defects, and finally proceed with sensor structure fabrication.

The shape differences of etch pits on SiC substrates are determined jointly by surface polarity, dislocation type, and the oxidation‑removal cycle. These pits have no impact on power device performance, but they adversely affect the stress distribution and surface quality of pressure sensors. By precisely controlling etching temperature and time, adopting single‑side protected etching, applying post‑CMP treatment, and exploring additive processes, the etch morphology can be effectively improved to meet the requirements of sensor applications.

Whether you need 4H-SiC wafers for research or for industrial applications, please contact us email at [email protected] and [email protected].

 

References:

1. Yang, G., Xu, L., Cui, C., Pi, X., Yang, D., & Wang, R. (2024). Anisotropic etching mechanisms of 4H-SiC: Experimental and first-principles insights. Journal of Semiconductors, 45(1), 012502.
2. Sumakeris, J. J., Leonard, R. T., Deyneka, E., Khlebnikov, Y., Powell, A. R., Seaman, J., … & Balkas, E. (2016, June). Dislocation characterization in 4H-SiC crystals. In Materials Science Forum (Vol. 858, pp. 393-396). Trans Tech Publications Ltd.
3. Syväjärvi, M., Yakimova, R., & Janzén, E. (2000). Anisotropic etching of SiC. Journal of the Electrochemical Society, 147(9), 3519-3522.