SOI Wafer

In the evolution of contemporary semiconductor technology, Silicon on Insulator (SOI) has transformed from a specialized technique into a critical material platform that underpins high‑performance computing, low‑power communication, MEMS sensing, and even quantum device research. For researchers, SOI wafer is not merely a substrate for experiments but a “testbed” for exploring novel physical effects and pushing performance limits.

Fig. 1 Typical structure of an SOI wafer and device applications

1. Why Choose an SOI Wafer? – Core Advantages from Device Physics

The fundamental structure of an SOI wafer delivers multiple irreplaceable device‑level advantages. Compared with conventional bulk‑silicon CMOS technology, SOI technology brings a radical change in device isolation schemes.

• Latch‑up elimination: The SOI structure achieves complete dielectric isolation between devices, with no parasitic thyristor paths (see Fig. 2), significantly improving circuit reliability.
• Reduced parasitic capacitance and higher speed: The buried oxide layer (BOX) isolates the device layer from the substrate, substantially lowering the source/drain parasitic capacitance to the substrate (approximately 1/3 of that in bulk silicon).
• Excellent radiation hardness: The active volume is greatly reduced, leading to a marked decrease in photocurrent induced by ionizing radiation.
• Wide temperature operation (up to >300 °C): In fully depleted SOI devices at high temperatures, the off‑state leakage current is dominated by generation current (proportional to n_i (T) rather than by diffusion current (proportional to  n_i² (T) as in bulk silicon, yielding leakage currents 3–4 orders of magnitude lower than those of bulk devices.
• Supports extreme scaling: Ultrathin device layers (≤20nm) combined with multi‑gate architectures (FinFET, Ω‑FET, GAA) effectively suppress short‑channel effects, enabling gate lengths to be scaled below 10 nm.

Fig. 2 Structural comparison between bulk‑silicon CMOS and SOI CMOS

2. Mainstream Manufacturing Routes and Technical Challenges for SOI Wafers

The final device performance of an SOI wafer is highly dependent on the choice of fabrication process. Currently, the industry‑standard preparation techniques – including SIMOX (Separation by IMplanted OXygen), Smart Cut™ (smart‑cutting), and BESOI (Bond and Etch‑back SOI) – each rely on different physical mechanisms and offer differentiated advantages in BOX quality, device‑layer defect density, and thickness uniformity, making them suitable for applications ranging from ultrathin FD‑SOI to thick‑film MEMS.

2.1 SIMOX (Separation by Implanted Oxygen)

A buried oxide layer is formed by high‑dose oxygen ion implantation followed by high‑temperature annealing. The later‑developed ITOX (Internal Thermal Oxidation) process can effectively eliminate “silicon pipes” defects and improve the stoichiometry of the BOX layer.

Fig. 3 SIMOX process principle and cross‑sectional micrograph

2.2 Smart Cut™ Technology

Through hydrogen ion implantation and wafer bonding, the device layer is transferred with high precision. This is currently the mainstream method for producing high‑quality SOI wafers. It enables precise control of the device‑layer thickness (4nm – 1.5μm) and BOX thickness (5nm – 5μm), while the seed wafer can be reused, significantly reducing cost.

Fig. 4 Smart Cut™ process steps and microstructures of the implanted region

2.3 Eltran®, BSOI, and BESOI Technologies

• Eltran®: Uses porous silicon as a separation layer; after epitaxial growth of single‑crystal silicon, the layer is transferred. The device layer suffers no ion‑implantation damage and is free from Crystal Originated Particles (COPs) defects.
• BSOI / BESOI: Suitable for thick device layers (>10μm) for applications such as power devices and MEMS structures. BESOI introduces a boron‑ or germanium‑doped etch‑stop layer to achieve highly uniform thin layers.

Fig. 5 Schematic illustrations of (a) Eltran®, (c) BSOI, and (d) BESOI processes

3. Characterization of SOI Wafers

Differences in research results often originate from subtle fluctuations in substrate quality. Therefore, in research‑grade SOI wafer applications, systematic structural characterization and electrical testing have become essential prerequisites to verify whether the material meets device fabrication requirements.

3.1 Structural Defect Characterization (HF Defects and Secco Defects)

Crystal defects in the device layer can propagate to the buried oxide layer, forming optically detectable defect points after HF etching. Secco etching preferentially attacks regions of stress concentration to reveal dislocations and other defects.

3.2 Electrical Characterization (Pseudo‑MOSFET, Hall Effect, and Four‑Point Probe)

For ultrathin device layers, conventional testing methods are limited. The pseudo‑MOSFET method, Hall effect measurements, and four‑point probe techniques are employed to extract key electrical parameters (mobility, threshold voltage, doping concentration, and interface state density).

4. SOI Device Architectures and Physical Effects for Cutting‑Edge Research

For academic users, silicon-on-insulator is not just a substrate but a platform for exploring novel device physics.

• Multi‑gate architectures (FinFET, Ω‑FET, GAA): By enhancing gate electrostatic control, short‑channel effects are effectively suppressed. Theory and experiments indicate that when the fin width (W_fin) is ≤2/3 of the gate length (L_g), an ideal subthreshold swing (~60mV/dec) can be achieved.
• Fully Depleted (FD) and Partially Depleted (PD) characteristics: FD‑SOI MOSFETs exhibit a steeper subthreshold swing (theoretical minimum 60mV/dec), allowing lower threshold voltages and lower‑power operation, while being free from the “kink effect.”
• Quantum confinement and volume inversion: When the device‑layer thickness is <10nm, carriers experience geometric quantum confinement (energy quantization leading to threshold‑voltage increase). In double‑gate structures with a moderately thick silicon film, “volume inversion” can occur, where carrier distribution is concentrated in the center of the film rather than at the interfaces, significantly reducing interface scattering and enhancing mobility.

5. SOI Wafers Available – Stable Material Support for Research

PAM-XIAMEN supplies a SOI wafers for R&D applications. The device‑layer thickness, buried‑oxide thickness, and doping type can all be flexibly configured according to research requirements. To obtain an SOI wafer price or technical consultation, please submit the contact form or send an email to [email protected]

SOI Wafer Specification – PAM07162026
Term	Parameters	Value
Final SOI Wafer	Diameter	100mm	150mm	200mm
	Orientation	(100), (110), (111)
	TTV	<5um
	BOW	<±30um
	Warp	<40um
	metal	<5E10(atoms/cm²)
	Light Point Defects (@0.2μm)	<50ea/wafer
	Area Count (@0.8μm)	<20ea/wafer
	Positioning	Flats or notch
SOI Layer	Thickness	0.1~300um
	Conductivity type	N, P
	Resistivity	0.001–100Ω·cm; ≥10,000Ω·cm
	SOI layer finish	polished
Buried Oxide Layer	Thickness	0.1~4um
Handle Wafer	Thickness	(400-525)±15um	(400-625)±15um	(400-725)±15um
	Orientation	(100), (110), (111)
	Conductivity type	N, P
	Growth method	CZ, MCZ or FZ
	Resistivity	0.001–100Ω·cm; ≥10,000Ω·cm
	Backside Finish	polished, etched, Oxide
	Laser mark	SEMI M12

Whether you need Semiconductor Wafers for research or for industrial applications, please contact us email at [email protected] and [email protected].

 

References:

1. Kim, T., & Lee, J. (2023). Fabrication and characterization of silicon-on-insulator wafers. Micro and Nano Systems Letters, 11(1), 15.
2. Rudenko, T. E., Nazarov, A. N., & Lysenko, V. S. (2020). The advancement of silicon-on-insulator (SOI) devices and their basic properties. Semiconductor Physics, Quantum Electronics & Optoelectronics, 23(3).