The most basic and key parameters of SiC epitaxial materials are the thickness and doping concentration uniformity.In fact, the epitaxial parameters mainly depend on the device design. For example, the epitaxial parameters are different according to the different voltage levels of the devices. Generally, when the low voltage is 600 V, the thickness of epitaxy we need may be about 6μm. For the medium voltage of 1200 ~ 1700, the thickness we need is 10 ~ 15 μm. If the voltage is >= 10000 volts, more than 100 μm may be needed. Therefore, with the increase of voltage capability, the epitaxial thickness increases, and the preparation of high-quality epitaxial wafers is more difficult, especially the defect control in the high-voltage field, which is also a great challenge.
Defects in SiC epitaxy
In fact, there are many defects in SiC epitaxy. Because of the different crystal, its defects are different from those of other crystals. His defects mainly include microtubule, triangle defect, carrot defect on the surface, and some special defects such as step aggregation.
Basically, many defects are directly copied from the substrate, so the quality of substrate and the level of processing are very important for epitaxial growth, especially for the control of defects.
SiC epitaxial defects are generally classified into fatal and non fatal one. Fatal defects, such as triangle defects and droppings, have an impact on all types of devices, including diodes, MOSFETs and bipolar devices. The biggest impact is the breakdown voltage, which can reduce the breakdown voltage by 20% or even 90%. Non fatal defects, such as some TSD and TED, may have no effect on the diode, and may have an impact on the life of MOS and bipolar devices, or have some effect of leakage, which will eventually affect the processing qualification rate of the device
To control the epitaxial defects of SiC, the first method is to select the substrate material carefully; the second is to select the equipment and localization; the third is to process technology.
Progress of SiC epitaxial technology
In the field of low and medium voltage, the core parameters thickness and doping concentration of epitaxial wafers can be relatively better. However, in the field of high voltage, there are still many difficulties to overcome, including thickness, uniformity of doping concentration, triangle defects and so on.
In the field of medium and low voltage applications, SiC epitaxial technology is relatively mature. It can basically meet the requirements of SBD, JBS, MOS and other devices in low and medium voltage. The above is a 10μm epitaxial wafer for 1200 V device application. Its thickness and doping concentration have reached a very good level, and the surface defects are also very good, which can reach less than 0.5 square meters.
In the field of high-voltage epitaxy, the development of epitaxial technology is relatively backward. For example, a 200 μm SiC epitaxial material on a 20000 V device has a lot of uniformity, thickness and concentration compared with the low-voltage difference described above, especially the uniformity of doping concentration. At the same time, there are many defects in the thick film required by high voltage devices, especially the triangular defects, which mainly affect the preparation of high current devices. A large current requires a large chip area. At the same time, its minority carrier lifetime is also relatively low.
In terms of high voltage, the types of devices tend to be used in bipolar devices, which require higher minority carrier lifetime. From the figure on the right, we can see that in order to achieve an ideal forward current, its minority carrier lifetime must be at least 5 μs or more. At present, the parameters of minority carrier lifetime of epitaxial wafers are about 1 ~ 2 μs, so there is no demand for high-voltage devices at present It also needs post-processing technology.