Powerway Wafer offers III-nitride GaN LED Epi wafer on flat or patterned Sapphire as listed below, which emits blue or green lights. The GaN LED market size is 50mm, 100mm, 150mm or 200mm. The GaN LED emission wavelength can reach 530nm.
A high crystal quality GaN can be gained by depositing a buffer layer at low temperatures. Because of such high quality GaN, the p-type GaN, p-n junction blue/UV-LED and room temperature stimulated emission are discovered.
1. Specifications of GaN Blue/Green LED Epi Wafer
100mm wafers of blue GaN LED epi layer on c-plane sapphire, 445-475nm (PAM-191010-GaN-LED);
100mm wafers of green GaN LED epi layer on c-plane sapphire, 510-530nm;
Item 3(PAM-190320-blue GaN LED wafer ):
Blue emitting GaN on sapphire commercial LED wafers with maximum output power and the backside polished, which is for compound semiconductor device manufacture;
2. Parameters of GaN LED Epi Wafer on Sapphire
The parameters of GaN LED epi wafer on sapphire are below:
|Cassette||No.||Wafer ID||Substrate||Wd Avg||Wd Std||FWHM Avg||Chip size||Vf（20ma）||IV（mcd）||IR Yield||ESD Yield (HBM 2000)|
3. GaN LED Epi Process
The basic principle of epitaxial growth is that on a substrate (mainly sapphire (Al2O3) and SiC, Si) heated to an appropriate temperature, gaseous substances In, Ga, Al, and P are transported to the surface of the substrate in a controlled manner. A specific single crystal thin film is grown. At present, the LED epitaxy growth technology mainly adopts MOCVD method.
The substrate material used by most companies now is sapphire (Al203) for GaN LED Epi wafer. Although it has a character mismatch of 13.8% with GaN, the GaN thin film material grown on the sapphire substrate will have a very high dislocation density. However, the cost is low, relatively mature technology, and good stability at high temperature.
4. FAQ for GaN LED Epi Wafer
Q1: What is the typical rms roughness of the polished sapphire backside surface?
Answer: It depends on your application.
Q2: Our application is to fabricate microLED devices using the epi-wafer and perform Laser Liftoff to release the devices for mass transfer and assembly. Could you kindly provide details of the thickness of each layer of the epi stack for both the Green and blue (such as total thickness of the epi-layer on sapphire, thickness of p-GaN, active region, n-GaN and the underlying u-GaN layer etc.)?
Answer: Yes, for laser liftoff application, it should be specific requirement on surface, for more information, please consult our engineer team: [email protected].
Q3: 1. These new wafers are 2 inch blue LED wafers on sapphire substrates?
2. These new wafers are annealed (activated) and backside polished so that I can use them straightaway?
3. These new LED wafers’ qualities (especially the output power) are the same or even better compared with the wafers I bought last time?
Answer: You requirement is: backside polished; annealed; for high power; if so, we recommend you new wafers, but it is 4”size: wavelength:475+/-5nm.
Q4: We need blue LED wafer for laser lift off(LLO) process.
If you have suitable specification wafer, we would like to get samples.
Could you give us information of spec.?
And if you have LLO experience, could you give us information?
Answer: We have some clients requesting LED wafer for laser lift off for micro LED application. For LLO, the wafers needs backside polished, which is some difficult, as during the process, it would be risky for scratch the surface.
There are two options:
Option1: LED wafer on flat sapphire, back side polished.
Option2: LED wafer on patterned sapphire, back side polished.
Q5: Do you think you could let us know if the p-GaN activation was done with in-situ anneal or ex-situ RTA process ?
Answer: We have already done a simple annealing when Mocvd is growing. This is what you call in-situ annealing, but the time is not long enough. So the chip will assist in annealing. Now all the chip processes are like this. My epitaxial wafer can go through the normal chip program.
I don’t know if the in-situ rta program you are referring to is annealed at the end of the chip with an annealing furnace. If so, then my LED/PSS epitaxial wafer does not go through this annealing.